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Entry  Fri Feb 22 11:46:17 2013, Yury Golod, DRS4 trigger, different polarity 

I need to synchronize two signals. These signals have a different polarity.

I can set triggers on different levels. But I can't set different polarity of triggers.

Now I can set (T1 and T2), I need to set (T1 and (not T2))

Is it possible?

 

           

d->SetTriggerLevel(-0.4,0.4,0.0,0.0,false);

d->EnableTrigger(1, 0);  // Enable trigger

d->SetTriggerSource(1<<8 | 1<<9);  // T1 and T2

 

file DRS.cpp:

int DRSBoard::SetTriggerLevel(double voltage1,double voltage2, double voltage3,double voltage4,bool negative)

{

      SetDAC(fDAC_TLEVEL1, voltage1/2 + 0.8);

      SetDAC(fDAC_TLEVEL2, voltage2/2 + 0.8);

 

    Reply  Fri Feb 22 11:56:57 2013, Stefan Ritt, DRS4 trigger, different polarity 

Yury Golod wrote:

I need to synchronize two signals. These signals have a different polarity.

I can set triggers on different levels. But I can't set different polarity of triggers.

Now I can set (T1 and T2), I need to set (T1 and (not T2))

Is it possible?

 

           

 

d->SetTriggerLevel(-0.4,0.4,0.0,0.0,false);

d->EnableTrigger(1, 0);  // Enable trigger

d->SetTriggerSource(1<<8 | 1<<9);  // T1 and T2

 

file DRS.cpp:

int DRSBoard::SetTriggerLevel(double voltage1,double voltage2, double voltage3,double voltage4,bool negative)

{

      SetDAC(fDAC_TLEVEL1, voltage1/2 + 0.8);

      SetDAC(fDAC_TLEVEL2, voltage2/2 + 0.8);

 

There is no way to select different polarities, it is not implemented in the firmware. Like your digital oscilloscope has also only one polarity switch.

The only way to do it is to use a (passive) inverter, so that you have two signals of the same polarity. Something like this:

http://www.phillipsscientific.com/pdf/460ds.pdf

 

Entry  Wed Feb 13 16:58:40 2013, Martin Petriska, Nonuniform sampling 

 Are there any plans to include reconstruction of nonuniform sampling  in DRS4 to get uniformly sampled data?

Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel

and plan to implement it, but may be somebody has it done before me.

 

    Reply  Wed Feb 13 17:03:53 2013, Stefan Ritt, Nonuniform sampling 

Martin Petriska wrote:

 Are there any plans to include reconstruction of nonuniform sampling  in DRS4 to get uniformly sampled data?

Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel

and plan to implement it, but may be somebody has it done before me.

 

Interesting paper. I was not aware of this method. Sounds interesting. AFAIK, nobody has implemented it so far.

My (old) plan was to linearly interpolate samples (something you could do in an FPGA as well), but this will introduce (small) errors. The next best thing would be to do some spline interpolation, but this is time consuming and not suited for an FPGA.

If you get good results with the method above, please let others know about it.

/Stefan 

Entry  Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors 

Hi Stefan,

A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?

 Best,

Jinhong

    Reply  Thu Dec 27 09:49:17 2012, Stefan Ritt, variation of sampling capacitors 

Jinhong Wang wrote:

Hi Stefan,

A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?

 Best,

Jinhong 

The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.

Stefan

       Reply  Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors 

Stefan Ritt wrote:

Jinhong Wang wrote:

Hi Stefan,

A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?

 Best,

Jinhong 

The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.

Stefan

 Great to know this! Thanks~

Jinhong

          Reply  Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors 

Jinhong Wang wrote:

Stefan Ritt wrote:

Jinhong Wang wrote:

Hi Stefan,

A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?

 Best,

Jinhong 

The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.

Stefan

 Great to know this! Thanks~

Jinhong

 Hi Dr. Stefan,

So the sampling capacitors store the input voltage instead of the charge. What about the readout circuits? I saw there is a buffer followed each sampling capacitor. Do you buffer the charge (like a charge sensitive amplifier)  or the voltage? From Fig.12, 14 in datasheet, it seems most probably the readout is a charging or discharging of a capacitor. Could you please add some comments on this? 

Cheers,

Jinhong

             Reply  Tue Feb 5 14:38:35 2013, Stefan Ritt, variation of sampling capacitors 

Jinhong Wang wrote:

Hi Dr. Stefan,

So the sampling capacitors store the input voltage instead of the charge. What about the readout circuits? I saw there is a buffer followed each sampling capacitor. Do you buffer the charge (like a charge sensitive amplifier)  or the voltage? From Fig.12, 14 in datasheet, it seems most probably the readout is a charging or discharging of a capacitor. Could you please add some comments on this? 

Cheers,

Jinhong

The buffer buffers the voltage, not the charge. The curves in Fig. 12, 14 indicate that the voltage followers take some time until they settle. 

Stefan

Entry  Thu Dec 6 09:23:36 2012, Martin Petriska, EVM rev4 board trigger change and drs_example 

 I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting for trigger (rev.3 is working). How to do in drs_exam.cpp for example triggering on Ch0 && CH1 ?

Software 4.0.0, windows version.

Here is old trigger initialisation: 

b->EnableTrigger(0,1);

b->SetTriggerSource(0);

b->SetTriggerLevel(0.25, false);

b->SetTriggerDelayNs(0);

 

Btw. Is it possible to set up different trigger Levels for each channel ?

 

(If there is some interest here is my code in Qt, still aplha) http://sourceforge.net/p/qtpals/code

    Reply  Fri Dec 14 21:49:29 2012, Stefan Ritt, EVM rev4 board trigger change and drs_example 

Martin Petriska wrote:

 I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting for trigger (rev.3 is working). How to do in drs_exam.cpp for example triggering on Ch0 && CH1 ?

Software 4.0.0, windows version.

Here is old trigger initialisation: 

b->EnableTrigger(0,1);

b->SetTriggerSource(0);

b->SetTriggerLevel(0.25, false);

b->SetTriggerDelayNs(0);

 

Btw. Is it possible to set up different trigger Levels for each channel ?

 

(If there is some interest here is my code in Qt, still aplha) http://sourceforge.net/p/qtpals/code

Sorry the late reply.

In V4, triggering has changed. You can trigger now on an OR or AND of channels. Therefore you have to supply a bitmask, where the 1st bit = CH1, 2nd bit = CH2 and so on. Have a look at the most recent drs_exam. It contains code:

 

   /* use following lines to enable hardware trigger on CH1 at 50 mV positive edge */
   if (b->GetBoardType() == 8) {     // Evaluaiton Board V4 
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<0);        // set CH1 as source
   } else {                          // Evaluation Board V3
      b->EnableTrigger(0, 1);           // lemo off, analog trigger on
      b->SetTriggerSource(0);           // use CH1 as source
   } 

So if you want CH1 && CH2, you look at the source code of SetTriggerSource. It contains

 

      // Set trigger configuration
   // OR  0=CH1, 1=CH2, 2=CH3, 3=CH4, 4=EXT
   // AND 8=CH1, 9=CH2, 10=CH3, 11=CH4, 12=EXT

 

So an AND between CH1 and CH2 needs a

    b->SetTriggerSource(1<<8 | 1<<9);

Your code looks interesting. Do you have a screenshot or can you explain what it does? 

Entry  Thu Dec 13 12:03:29 2012, Evgeni, DRS-4 trigger 

How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). 

    Reply  Thu Dec 13 12:14:35 2012, Stefan Ritt, DRS-4 trigger 

Evgeni wrote:

How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). 

Sorry, I don't understand that question. The DRS4 Evaluation board input signal range is 1V. If you have larger signals, you have to attenuante them externally.

/Stefan 

       Reply  Thu Dec 13 19:49:47 2012, Evgeni, DRS-4 trigger 

 

Stefan Ritt wrote:

 

Evgeni wrote:

How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). 

 

Sorry, I don't understand that question. The DRS4 Evaluation board input signal range is 1V. If you have larger signals, you have to attenuante them externally.

/Stefan 

 

 

Can I adjust the internal trigger DRS oscilloscope for signal extraction 0.5 volts (for example) from any of the four channels. In our case, there is a lot of noise with low amplitude, which must be removed during the registration. We need to record the individual pulses of higher amplitude than the noise. So we want to use the internal trigger DRS oscilloscope to cut this noise by setting up its threshold amplitude noise.

          Reply  Fri Dec 14 08:42:53 2012, Stefan Ritt, DRS-4 trigger DRSOsc.png

Evgeni wrote:

 

Stefan Ritt wrote:

 

Evgeni wrote:

How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). 

 

Sorry, I don't understand that question. The DRS4 Evaluation board input signal range is 1V. If you have larger signals, you have to attenuante them externally.

/Stefan 

 

 

Can I adjust the internal trigger DRS oscilloscope for signal extraction 0.5 volts (for example) from any of the four channels. In our case, there is a lot of noise with low amplitude, which must be removed during the registration. We need to record the individual pulses of higher amplitude than the noise. So we want to use the internal trigger DRS oscilloscope to cut this noise by setting up its threshold amplitude noise.

 

 Sure, you can set the trigger level with the vertical slider (see attached figure). The trigger level works form -0.5V to +0.5V. Just like with a normal oscilloscope. I thought this would be obvious...

             Reply  Fri Dec 14 10:07:54 2012, Evgeni, DRS-4 trigger 

 

Stefan Ritt wrote:

 

Evgeni wrote:

 

Stefan Ritt wrote:

 

Evgeni wrote:

How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). 

 

Sorry, I don't understand that question. The DRS4 Evaluation board input signal range is 1V. If you have larger signals, you have to attenuante them externally.

/Stefan 

 

 

Can I adjust the internal trigger DRS oscilloscope for signal extraction 0.5 volts (for example) from any of the four channels. In our case, there is a lot of noise with low amplitude, which must be removed during the registration. We need to record the individual pulses of higher amplitude than the noise. So we want to use the internal trigger DRS oscilloscope to cut this noise by setting up its threshold amplitude noise.

 

 

 Sure, you can set the trigger level with the vertical slider (see attached figure). The trigger level works form -0.5V to +0.5V. Just like with a normal oscilloscope. I thought this would be obvious...

 

    That's it? Thank you for your comprehensive answer.

    Reply  Fri Dec 14 10:07:14 2012, Evgeni, DRS-4 trigger 

 

Evgeni wrote:

How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). 

 

 

Entry  Tue Dec 4 09:24:22 2012, Zhongwei Du, Question of drs4 using 

When Denable and Dwrite is high , the voltage of PLLOUT is 0 V.  And  the Dtap is turn high with no delay when the Denable turns high.

After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first about 100 cells is rise or fall  and the last 900 cells is out of the range of ADC.

So how should I do for debugging the drs4 now.

    Reply  Tue Dec 4 09:39:44 2012, Stefan Ritt, Question of drs4 using 

Zhongwei Du wrote:

When Denable and Dwrite is high , the voltage of PLLOUT is 0 V.  And  the Dtap is turn high with no delay when the Denable turns high.

After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first about 100 cells is rise or fall  and the last 900 cells is out of the range of ADC.

So how should I do for debugging the drs4 now.

The first thing to make work is to have DTAP oscillating with fsamp/2048. Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. If not, double check all supply voltages, and especially all soldering points. The QFN package is a bit hard to solder.

/Stefan 

       Reply  Tue Dec 4 09:50:11 2012, Zhongwei Du, Question of drs4 using 

Stefan Ritt wrote:

Zhongwei Du wrote:

When Denable and Dwrite is high , the voltage of PLLOUT is 0 V.  And  the Dtap is turn high with no delay when the Denable turns high.

After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first about 100 cells is rise or fall  and the last 900 cells is out of the range of ADC.

So how should I do for debugging the drs4 now.

The first thing to make work is to have DTAP oscillating with fsamp/2048. Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. If not, double check all supply voltages, and especially all soldering points. The QFN package is a bit hard to solder.

/Stefan 

 "Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. "

In this process ,  should i config any registers( WSR,WCR,CR  ) ?

          Reply  Tue Dec 4 09:55:43 2012, Stefan Ritt, Question of drs4 using 

Zhongwei Du wrote:

Stefan Ritt wrote:

Zhongwei Du wrote:

When Denable and Dwrite is high , the voltage of PLLOUT is 0 V.  And  the Dtap is turn high with no delay when the Denable turns high.

After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first about 100 cells is rise or fall  and the last 900 cells is out of the range of ADC.

So how should I do for debugging the drs4 now.

The first thing to make work is to have DTAP oscillating with fsamp/2048. Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. If not, double check all supply voltages, and especially all soldering points. The QFN package is a bit hard to solder.

/Stefan 

 "Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. "

In this process ,  should i config any registers( WSR,WCR,CR  ) ?

After power-up reset, these registers are all set to "1", which should be ok to start.

BTW, Jinhong Wang <wangjinh@mail.ustc.edu.cn> from your institute hast the chip correctly working. Maybe he can help you in a more direct way than I can.

  

Entry  Mon Dec 3 08:32:28 2012, Gyuhee Kim, Another question about using multi boards. 

 Hi.

 

I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!)

And here is another question. I made two external triggers and try to acquire coincidence data using two boards. but DRS Oscilloscope program can connect only one board and don`t acquire both of them simultaneously.

So I tried to use two computer for each board separately, but, well, you already know, I failed to acquire because two computers don`t promise to synchronize the two boards acquisition.

Is there any method to solve this problem?

 

1. I want to acquire coincidence data from the two DRS 4 Evaluation board V4 simultaneosly.

2. I have external trigger to provide the two boards at the same time.

3. How can I get data from the two boards?

 

Best regards.

Gyuhee.

    Reply  Mon Dec 3 09:18:09 2012, Stefan Ritt, Another question about using multi boards. 

Gyuhee Kim wrote:

 Hi.

 

I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!)

And here is another question. I made two external triggers and try to acquire coincidence data using two boards. but DRS Oscilloscope program can connect only one board and don`t acquire both of them simultaneously.

So I tried to use two computer for each board separately, but, well, you already know, I failed to acquire because two computers don`t promise to synchronize the two boards acquisition.

Is there any method to solve this problem?

 

1. I want to acquire coincidence data from the two DRS 4 Evaluation board V4 simultaneosly.

2. I have external trigger to provide the two boards at the same time.

3. How can I get data from the two boards?

 

Best regards.

Gyuhee.

You have to write your own program. DRS Oscilloscope does not (yet) support this. Take drs_exam.cpp as a starting point and try to extend it to two boards. One tricky point is that the external trigger may only fire AFTER the two boards have been read out. So you need some means of re-enabling the external trigger after you read out both boards.

Stefan 

       Reply  Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards. 

Stefan Ritt wrote:

Gyuhee Kim wrote:

 Hi.

 

I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!)

And here is another question. I made two external triggers and try to acquire coincidence data using two boards. but DRS Oscilloscope program can connect only one board and don`t acquire both of them simultaneously.

So I tried to use two computer for each board separately, but, well, you already know, I failed to acquire because two computers don`t promise to synchronize the two boards acquisition.

Is there any method to solve this problem?

 

1. I want to acquire coincidence data from the two DRS 4 Evaluation board V4 simultaneosly.

2. I have external trigger to provide the two boards at the same time.

3. How can I get data from the two boards?

 

Best regards.

Gyuhee.

You have to write your own program. DRS Oscilloscope does not (yet) support this. Take drs_exam.cpp as a starting point and try to extend it to two boards. One tricky point is that the external trigger may only fire AFTER the two boards have been read out. So you need some means of re-enabling the external trigger after you read out both boards.

Stefan 

That`s very bad news for me. I don`t have much time to study & write C programming...

Anyway, Thank you very much Stefan.

 

Best regards.

Gyuhee.

Entry  Wed Nov 28 16:54:46 2012, Stefan Ritt, DRS Oscilloscope for Raspberry Pi and Mac OSX 10.8 screenshot_pi.png

I made a pre-compiled package for Mac OSX 10.8 (Mountain Lion), so one should be able to install the DRS Oscilloscope software with one mouse click on a recent Mac.

The Makefile in the tar ball now also supports OSX 10.8, so one could even compile it from the sources on a Mac, after libusb-1.0 and wxWidgets have been installed. That might then also work on older versions of OSX.

In addition, the software has been adaptes so that it compiles nicely on a Raspberry Pi (http://www.raspberrypi.org), a screenshot has been attached. Together with a Raspberry Pi and an old screen, the evaluation board is one of the cheapest available oscilloscopes.

 

 

Entry  Wed Nov 21 08:34:52 2012, Gyuhee Kim, Question for using Multi board 

 Hi.

 

I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ.

But there is no option for multi board use. I just only find the multi board trigger mode check button on DRS4 Oscilloscope program, but I couldn`t check. 

Is there any method to use multi board?

 

Best regards.

Gyuhee.

    Reply  Wed Nov 21 08:38:26 2012, Stefan Ritt, Question for using Multi board 

Gyuhee Kim wrote:

 Hi.

 

I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ.

But there is no option for multi board use. I just only find the multi board trigger mode check button on DRS4 Oscilloscope program, but I couldn`t check. 

Is there any method to use multi board?

 

Best regards.

Gyuhee.

This mode is not yet implemented in firmware. Maybe I find some time towards the end of this year to add this. At the moment, you have to build and external trigger to synchronize the two boards. There are also 16-channel boards on the market where you would not need a multi-board mode. Just Google for "DT5742".

/Stefan

       Reply  Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board 

Stefan Ritt wrote:

Gyuhee Kim wrote:

 Hi.

 

I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ.

But there is no option for multi board use. I just only find the multi board trigger mode check button on DRS4 Oscilloscope program, but I couldn`t check. 

Is there any method to use multi board?

 

Best regards.

Gyuhee.

This mode is not yet implemented in firmware. Maybe I find some time towards the end of this year to add this. At the moment, you have to build and external trigger to synchronize the two boards. There are also 16-channel boards on the market where you would not need a multi-board mode. Just Google for "DT5742".

/Stefan

 Thanks Stefan.

I will build external trigger system. 

Entry  Mon Oct 29 18:30:28 2012, Martin Petriska, GetWave 

 I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) etc...is used. Is there primary (cell) calibration, secondary calibration (Readout) and remove Spikes used, as in DRS Oscilloscope application?

    Reply  Tue Nov 13 11:26:32 2012, Stefan Ritt, GetWave 

Martin Petriska wrote:

 I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) etc...is used. Is there primary (cell) calibration, secondary calibration (Readout) and remove Spikes used, as in DRS Oscilloscope application?

 Yes, yes, no. To get spike removals, you need the function RemoveSpikes from Osci.cpp in the DRSOsc project.

Entry  Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware 

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point? Or is there any drs4_eval4_app.vhd missing in the source files?

 

thanks

 

Hongwei

    Reply  Thu Nov 1 20:17:42 2012, Stefan Ritt, DRS4 firmware drs4_eval4_app.vhd

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

       Reply  Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware 

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

          Reply  Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware 

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

             Reply  Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware drs4_eval4.vhd

hongwei yang wrote:

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

 Here it is.

                Reply  Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware 

Stefan Ritt wrote:

hongwei yang wrote:

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

 Here it is.

 Thanks. have a good day

Entry  Fri Oct 12 14:06:04 2012, Moritz von Witzleben, DRS abbreviation 

Hello,

what is the abbreviation of DRS?

Thanks and kind Regards,

Moritz

    Reply  Fri Oct 12 14:09:37 2012, Stefan Ritt, DRS abbreviation 

Moritz von Witzleben wrote:

Hello,

what is the abbreviation of DRS?

Thanks and kind Regards,

Moritz

Domino Ring Sampler. 

Entry  Thu Oct 4 20:50:36 2012, Zach Miller, DRS5 

Hi,

Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release date?"

Thanks for your time,

Zach Miller

    Reply  Thu Oct 4 20:59:18 2012, Stefan Ritt, DRS5 

Zach Miller wrote:

Hi,

Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release date?"

Thanks for your time,

Zach Miller

You mix up two things: The DRS5 chip is a new device with improved samling speed (10 GSPS) and lower dead time. This chip might come in 2-3 years. The 16-input board you mentioned is a DAQ board based on the DRS4 chip. This board well be operational beginning of 2013 as a prototype. It is not clear however at this point in which way this board will be made available for public. Maybe we will license this to industry. The design is however pretty much defined: 16 channels with gain 0.1-100, 1 GHz Bandwidth, Gigabit Ethernet output, and multi-board capabilities. Trigger on each channel with logical combinations. 80 MSPS continuous sampling (in addition to the DRS4 sampling). Each channel can be biased 0-210 V for SiPMT or APD power. A 19" 3 HE crate will host 16 boards with 256 channels.

/Stefan

       Reply  Thu Oct 4 21:07:27 2012, Zach Miller, DRS5 

Stefan Ritt wrote:

Zach Miller wrote:

Hi,

Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release date?"

Thanks for your time,

Zach Miller

You mix up two things: The DRS5 chip is a new device with improved samling speed (10 GSPS) and lower dead time. This chip might come in 2-3 years. The 16-input board you mentioned is a DAQ board based on the DRS4 chip. This board well be operational beginning of 2013 as a prototype. It is not clear however at this point in which way this board will be made available for public. Maybe we will license this to industry. The design is however pretty much defined: 16 channels with gain 0.1-100, 1 GHz Bandwidth, Gigabit Ethernet output, and multi-board capabilities. Trigger on each channel with logical combinations. 80 MSPS continuous sampling (in addition to the DRS4 sampling). Each channel can be biased 0-210 V for SiPMT or APD power. A 19" 3 HE crate will host 16 boards with 256 channels.

/Stefan

 Thanks, Stefan. That was the information we were looking for.

Cheers.

-Zach

Entry  Tue Aug 28 17:52:45 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 

Hi,

I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt to build the drs-4.0.0, I get this similar error:

src/DOScreen.cpp:332:39: error: call of overloaded ‘Append(int)’ is ambiguous
 

This section of code is different than what the previous thread was correcting, and though I attempted to apply the logic of the old thread, I haven't fixed this yet.

The following is the code for that section:

-----

329  for (int i=0 ; i<5 ; i++)
330       if (tc & (1<<(i+8))) {
331            if (i < 4)
332              wxst1.Append(wxT('1'+i));
333            else
334              wxst1.Append(wxT('E'));
335           wxst1.Append(wxT('&'));
336        }
337      if (wxst1.Length() > 0)
338         wxst1 = wxst1.Left(wxst1.Length()-1);
339      wxst1.Append(wxT(')'));

------

I've attempted a few fixes, but unfortunately, my understanding of the code is not great, and I haven't managed to fix this yet. Any help would be appreciated.

Thanks,

Zach Miller

    Reply  Wed Aug 29 10:52:44 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp 

Zach Miller wrote:

Hi,

I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt to build the drs-4.0.0, I get this similar error:

src/DOScreen.cpp:332:39: error: call of overloaded ‘Append(int)’ is ambiguous
 

This section of code is different than what the previous thread was correcting, and though I attempted to apply the logic of the old thread, I haven't fixed this yet.

The following is the code for that section:

-----

329  for (int i=0 ; i<5 ; i++)
330       if (tc & (1<<(i+8))) {
331            if (i < 4)
332              wxst1.Append(wxT('1'+i));
333            else
334              wxst1.Append(wxT('E'));
335           wxst1.Append(wxT('&'));
336        }
337      if (wxst1.Length() > 0)
338         wxst1 = wxst1.Left(wxst1.Length()-1);
339      wxst1.Append(wxT(')'));

------

I've attempted a few fixes, but unfortunately, my understanding of the code is not great, and I haven't managed to fix this yet. Any help would be appreciated.

Thanks,

Zach Miller

Just put (char) in front of wxT(...), like

   if (tc > 0) {

      wxString wxst1, wxst2;

      wxst1.Append((char)wxT('('));

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<i)) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('|'));

         }

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<(i+8))) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('&'));

         }

      if (wxst1.Length() > 0)

         wxst1 = wxst1.Left(wxst1.Length()-1);

      wxst1.Append((char) wxT(')')); 

       Reply  Wed Aug 29 16:42:42 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 

Stefan Ritt wrote:

Zach Miller wrote:

Hi,

I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt to build the drs-4.0.0, I get this similar error:

src/DOScreen.cpp:332:39: error: call of overloaded ‘Append(int)’ is ambiguous
 

This section of code is different than what the previous thread was correcting, and though I attempted to apply the logic of the old thread, I haven't fixed this yet.

The following is the code for that section:

-----

329  for (int i=0 ; i<5 ; i++)
330       if (tc & (1<<(i+8))) {
331            if (i < 4)
332              wxst1.Append(wxT('1'+i));
333            else
334              wxst1.Append(wxT('E'));
335           wxst1.Append(wxT('&'));
336        }
337      if (wxst1.Length() > 0)
338         wxst1 = wxst1.Left(wxst1.Length()-1);
339      wxst1.Append(wxT(')'));

------

I've attempted a few fixes, but unfortunately, my understanding of the code is not great, and I haven't managed to fix this yet. Any help would be appreciated.

Thanks,

Zach Miller

Just put (char) in front of wxT(...), like

   if (tc > 0) {

      wxString wxst1, wxst2;

      wxst1.Append((char)wxT('('));

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<i)) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('|'));

         }

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<(i+8))) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('&'));

         }

      if (wxst1.Length() > 0)

         wxst1 = wxst1.Left(wxst1.Length()-1);

      wxst1.Append((char) wxT(')')); 

 Hi Stefan,

Thanks for the response. I have tried that and it fixes all the lines except the ones that have:

wxst1.Append((char) (wxT('1'+i)));

Those lines still don't compile for me. I've also tried: wxst1.Append((char) (wxT('1'+(char)i))); and wxst1.Append((char) (wxT((char)'1'+i))); as well as a few other combinations of (char) and Append.

I get the same error of: "Call of overloaded "Append(int)" is ambiguous."

Any other help would be greatly appreciated. Thanks!

-Zach

          Reply  Wed Aug 29 16:45:36 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp 

Zach Miller wrote:

Stefan Ritt wrote:

Zach Miller wrote:

Hi,

I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt to build the drs-4.0.0, I get this similar error:

src/DOScreen.cpp:332:39: error: call of overloaded ‘Append(int)’ is ambiguous
 

This section of code is different than what the previous thread was correcting, and though I attempted to apply the logic of the old thread, I haven't fixed this yet.

The following is the code for that section:

-----

329  for (int i=0 ; i<5 ; i++)
330       if (tc & (1<<(i+8))) {
331            if (i < 4)
332              wxst1.Append(wxT('1'+i));
333            else
334              wxst1.Append(wxT('E'));
335           wxst1.Append(wxT('&'));
336        }
337      if (wxst1.Length() > 0)
338         wxst1 = wxst1.Left(wxst1.Length()-1);
339      wxst1.Append(wxT(')'));

------

I've attempted a few fixes, but unfortunately, my understanding of the code is not great, and I haven't managed to fix this yet. Any help would be appreciated.

Thanks,

Zach Miller

Just put (char) in front of wxT(...), like

   if (tc > 0) {

      wxString wxst1, wxst2;

      wxst1.Append((char)wxT('('));

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<i)) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('|'));

         }

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<(i+8))) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('&'));

         }

      if (wxst1.Length() > 0)

         wxst1 = wxst1.Left(wxst1.Length()-1);

      wxst1.Append((char) wxT(')')); 

 Hi Stefan,

Thanks for the response. I have tried that and it fixes all the lines except the ones that have:

wxst1.Append((char) (wxT('1'+i)));

Those lines still don't compile for me. I've also tried: wxst1.Append((char) (wxT('1'+(char)i))); and wxst1.Append((char) (wxT((char)'1'+i))); as well as a few other combinations of (char) and Append.

I get the same error of: "Call of overloaded "Append(int)" is ambiguous."

Any other help would be greatly appreciated. Thanks!

-Zach

wxst1.Append((char) (wxT((char)('1'+i))));     maybe ??? 

             Reply  Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 

Stefan Ritt wrote:

Zach Miller wrote:

Stefan Ritt wrote:

Zach Miller wrote:

Hi,

I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt to build the drs-4.0.0, I get this similar error:

src/DOScreen.cpp:332:39: error: call of overloaded ‘Append(int)’ is ambiguous
 

This section of code is different than what the previous thread was correcting, and though I attempted to apply the logic of the old thread, I haven't fixed this yet.

The following is the code for that section:

-----

329  for (int i=0 ; i<5 ; i++)
330       if (tc & (1<<(i+8))) {
331            if (i < 4)
332              wxst1.Append(wxT('1'+i));
333            else
334              wxst1.Append(wxT('E'));
335           wxst1.Append(wxT('&'));
336        }
337      if (wxst1.Length() > 0)
338         wxst1 = wxst1.Left(wxst1.Length()-1);
339      wxst1.Append(wxT(')'));

------

I've attempted a few fixes, but unfortunately, my understanding of the code is not great, and I haven't managed to fix this yet. Any help would be appreciated.

Thanks,

Zach Miller

Just put (char) in front of wxT(...), like

   if (tc > 0) {

      wxString wxst1, wxst2;

      wxst1.Append((char)wxT('('));

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<i)) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('|'));

         }

      for (int i=0 ; i<5 ; i++)

         if (tc & (1<<(i+8))) {

            if (i < 4)

               wxst1.Append((char) (wxT('1'+i)));

            else

               wxst1.Append((char) wxT('E'));

            wxst1.Append((char) wxT('&'));

         }

      if (wxst1.Length() > 0)

         wxst1 = wxst1.Left(wxst1.Length()-1);

      wxst1.Append((char) wxT(')')); 

 Hi Stefan,

Thanks for the response. I have tried that and it fixes all the lines except the ones that have:

wxst1.Append((char) (wxT('1'+i)));

Those lines still don't compile for me. I've also tried: wxst1.Append((char) (wxT('1'+(char)i))); and wxst1.Append((char) (wxT((char)'1'+i))); as well as a few other combinations of (char) and Append.

I get the same error of: "Call of overloaded "Append(int)" is ambiguous."

Any other help would be greatly appreciated. Thanks!

-Zach

wxst1.Append((char) (wxT((char)('1'+i))));     maybe ??? 

 Aha!

wxst1.Append((char) (wxT('1'+i)));

That one actually works as you initially thought, but you my editor was being picky of (char)wxt... instead of (char) (wxt....). For some reason, it has to have the extra set of parentheses around wxt(). Thank You!

Entry  Wed Aug 1 17:42:32 2012, Mayank S. Rajguru, Calculation of loop filter parameters (R,C1and C1) for 1 GHz 

 Hi,

we are planning to use the DRS4 in our board for 1 GHz sampling and digitization.

I have seen in the data sheet that "For the PLL to work, an external loop filter is required. This filter ensures quick locking and stable operation at the desired sampling frequency".

What formula do you use to calculate the values of R, C1 and C2?

Can we use the same given value for different frequencies?

Thanks,

Mayak

    Reply  Mon Aug 6 02:44:00 2012, Stefan Ritt, Calculation of loop filter parameters (R,C1and C1) for 1 GHz 

Mayank S. Rajguru wrote:

 Hi,

we are planning to use the DRS4 in our board for 1 GHz sampling and digitization.

I have seen in the data sheet that "For the PLL to work, an external loop filter is required. This filter ensures quick locking and stable operation at the desired sampling frequency".

What formula do you use to calculate the values of R, C1 and C2?

Can we use the same given value for different frequencies?

Thanks,

Mayak

I never worked out an exact formula for the parameters. It also depends if you want a fast locking time, or a low phase jitter of the PLL. A good starting point are the values from the evaluation board:

R = 130 Ohm

C1 = 4.7 nF

C2 = 1 uF

They should work from 800 MHz to 5 GHz.

- Stefan 

Entry  Mon Jul 9 14:14:48 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows compile_log.txt

Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++ with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions will be helpful. Thank you.

    Reply  Tue Jul 10 13:15:00 2012, Stefan Ritt, Problem compiling drs_exam.cpp on windows 

Ivan Petrov wrote:

Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++ with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions will be helpful. Thank you.

I have no experience with dev-c++, so I cannot be of help here. The supported systems are Linux and Windows with MS Visual C++. But it looks like the problems are related to compiling wxWidgets, which actually you do NOT need for drs_exam.cpp. The wxWidgets library is only needed for the DRSOsc application. If you want to compile it anyhow, first learn how to compile standard WxWidgets applications from

http://www.wxwidgets.org/docs/tutorials/devcpp.htm

 

Best regards,

Stefan 

       Reply  Wed Jul 11 10:04:51 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows 

Stefan Ritt wrote:

Ivan Petrov wrote:

Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++ with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions will be helpful. Thank you.

I have no experience with dev-c++, so I cannot be of help here. The supported systems are Linux and Windows with MS Visual C++. But it looks like the problems are related to compiling wxWidgets, which actually you do NOT need for drs_exam.cpp. The wxWidgets library is only needed for the DRSOsc application. If you want to compile it anyhow, first learn how to compile standard WxWidgets applications from

http://www.wxwidgets.org/docs/tutorials/devcpp.htm

 

Best regards,

Stefan 

Ok, this was my bad, I added some unnecessary files to project. Drs_exam compiles well with ms vc++. Thanks!

Entry  Tue Mar 20 16:23:33 2012, Martin Petriska, triger for measuring time between pulses in channels 

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

    Reply  Tue Mar 20 16:33:50 2012, Stefan Ritt, triger for measuring time between pulses in channels 

Martin Petriska wrote:

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

It is muuuuch easier to upgrade to a V4 board!

Modification of firmware is not so easy. You have to learn and understand VHDL. Then, you have to add additional registers for this thresholds, which requires modification of the C library as well. The data inside the evaluation boards is not yet calibrated (this is only done on the C library), so you have an uncertainty of 30-40mV in this data. 

       Reply  Wed Mar 21 09:33:00 2012, Martin Petriska, triger for measuring time between pulses in channels 

Stefan Ritt wrote:

Martin Petriska wrote:

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

It is muuuuch easier to upgrade to a V4 board!

Modification of firmware is not so easy. You have to learn and understand VHDL. Then, you have to add additional registers for this thresholds, which requires modification of the C library as well. The data inside the evaluation boards is not yet calibrated (this is only done on the C library), so you have an uncertainty of 30-40mV in this data. 

Ok, except this, I would have a question regarding to the new trigering posibility in V4 board. At this time, I am using Ztec ZT4612 which has some pattern triger posibility. Output from this card is used as an external trigger. Regarding this I have found a problem. Pulses from PMT have about 5-8 ns width. But I need to measure time diferences between pulses in range from 0-50ns. Problem is, that coincidence between pulses is working only on short pulse area (5-8ns) when they are overlapped. Additionaly the result histogram of time diferences is proportional to the pulse shapes. I solve this problem enabling 20MHz LPF filter in ZT4612, so the pulses are wider and overlaped on larger area. But, how it is with the V4 board? Will it trigger if I have for example one 5ns pulse on begiinning of CH1 and second pulse for example 50 ns later on Ch2 with the same probability when pulses are in the same time position?

          Reply  Wed Mar 21 09:39:33 2012, Stefan Ritt, triger for measuring time between pulses in channels 

Martin Petriska wrote:

Stefan Ritt wrote:

Martin Petriska wrote:

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

It is muuuuch easier to upgrade to a V4 board!

Modification of firmware is not so easy. You have to learn and understand VHDL. Then, you have to add additional registers for this thresholds, which requires modification of the C library as well. The data inside the evaluation boards is not yet calibrated (this is only done on the C library), so you have an uncertainty of 30-40mV in this data. 

Ok, except this, I would have a question regarding to the new trigering posibility in V4 board. At this time, I am using Ztec ZT4612 which has some pattern triger posibility. Output from this card is used as an external trigger. Regarding this I have found a problem. Pulses from PMT have about 5-8 ns width. But I need to measure time diferences between pulses in range from 0-50ns. Problem is, that coincidence between pulses is working only on short pulse area (5-8ns) when they are overlapped. Additionaly the result histogram of time diferences is proportional to the pulse shapes. I solve this problem enabling 20MHz LPF filter in ZT4612, so the pulses are wider and overlaped on larger area. But, how it is with the V4 board? Will it trigger if I have for example one 5ns pulse on begiinning of CH1 and second pulse for example 50 ns later on Ch2 with the same probability when pulses are in the same time position?

No. 

             Reply  Wed Jun 20 10:40:21 2012, Ivan Petrov, triger for measuring time between pulses in channels 

Stefan Ritt wrote:

Martin Petriska wrote:

Stefan Ritt wrote:

Martin Petriska wrote:

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

It is muuuuch easier to upgrade to a V4 board!

Modification of firmware is not so easy. You have to learn and understand VHDL. Then, you have to add additional registers for this thresholds, which requires modification of the C library as well. The data inside the evaluation boards is not yet calibrated (this is only done on the C library), so you have an uncertainty of 30-40mV in this data. 

Ok, except this, I would have a question regarding to the new trigering posibility in V4 board. At this time, I am using Ztec ZT4612 which has some pattern triger posibility. Output from this card is used as an external trigger. Regarding this I have found a problem. Pulses from PMT have about 5-8 ns width. But I need to measure time diferences between pulses in range from 0-50ns. Problem is, that coincidence between pulses is working only on short pulse area (5-8ns) when they are overlapped. Additionaly the result histogram of time diferences is proportional to the pulse shapes. I solve this problem enabling 20MHz LPF filter in ZT4612, so the pulses are wider and overlaped on larger area. But, how it is with the V4 board? Will it trigger if I have for example one 5ns pulse on begiinning of CH1 and second pulse for example 50 ns later on Ch2 with the same probability when pulses are in the same time position?

No. 

Hello. I need to digitize pulses from two PMT. After pulse on first PMT I have to save all pulses from second PMT in range 200 ns (and starting pulse from the first, and time range between pulse from 1st PMT and pulses from 2nd PMT). Is it possible with DRS evaluation board?

                Reply  Wed Jun 20 12:45:05 2012, Stefan Ritt, triger for measuring time between pulses in channels 

Ivan Petrov wrote:

 

Hello. I need to digitize pulses from two PMT. After pulse on first PMT I have to save all pulses from second PMT in range 200 ns (and starting pulse from the first, and time range between pulse from 1st PMT and pulses from 2nd PMT). Is it possible with DRS evaluation board?

If you run at 2 GSPS, you have a time window of 500 ns like on an oscilloscope. If you trigger on 1st PMT, you will get the traces of all 4 inputs for the next 500 ns. So I guess this is what you want. 

                   Reply  Wed Jun 20 14:36:01 2012, Ivan Petrov, triger for measuring time between pulses in channels 

Stefan Ritt wrote:

Ivan Petrov wrote:

 

Hello. I need to digitize pulses from two PMT. After pulse on first PMT I have to save all pulses from second PMT in range 200 ns (and starting pulse from the first, and time range between pulse from 1st PMT and pulses from 2nd PMT). Is it possible with DRS evaluation board?

If you run at 2 GSPS, you have a time window of 500 ns like on an oscilloscope. If you trigger on 1st PMT, you will get the traces of all 4 inputs for the next 500 ns. So I guess this is what you want. 

 Ok. And, If I understand correctly, the main bottleneck in data readout is USB. I.e., theoretically maximum readout rate is 500 Hz. Is it true?

                      Reply  Wed Jun 20 14:44:38 2012, Stefan Ritt, triger for measuring time between pulses in channels 

Ivan Petrov wrote:

Stefan Ritt wrote:

Ivan Petrov wrote:

 

Hello. I need to digitize pulses from two PMT. After pulse on first PMT I have to save all pulses from second PMT in range 200 ns (and starting pulse from the first, and time range between pulse from 1st PMT and pulses from 2nd PMT). Is it possible with DRS evaluation board?

If you run at 2 GSPS, you have a time window of 500 ns like on an oscilloscope. If you trigger on 1st PMT, you will get the traces of all 4 inputs for the next 500 ns. So I guess this is what you want. 

 Ok. And, If I understand correctly, the main bottleneck in data readout is USB. I.e., theoretically maximum readout rate is 500 Hz. Is it true?

On the evaluation board, yes. This board is not optimized for high readout rate. If you do your own electronics, like GBit Ethernet, you could be much faster. 

                         Reply  Sat Jun 23 00:29:52 2012, Andrey Kuznetsov, triger for measuring time between pulses in channels 

Stefan Ritt wrote:

On the evaluation board, yes. This board is not optimized for high readout rate. If you do your own electronics, like GBit Ethernet, you could be much faster. 

 What is the readout rate via GBit Ethernet that you have achieved?

Where is the bottleneck in ethernet?

What is the proposed scheme by which the GBit Ethernet will be implemented, will the DRS4 Eval Board have to wait for the computer to respond before sending the data (wouldn't this make the readout much slower?), or will the DRS4 Eval Board keep sending the data to the computer?

                            Reply  Mon Jun 25 14:21:13 2012, Stefan Ritt, triger for measuring time between pulses in channels 

Andrey Kuznetsov wrote:

Stefan Ritt wrote:

On the evaluation board, yes. This board is not optimized for high readout rate. If you do your own electronics, like GBit Ethernet, you could be much faster. 

 What is the readout rate via GBit Ethernet that you have achieved?

Where is the bottleneck in ethernet?

What is the proposed scheme by which the GBit Ethernet will be implemented, will the DRS4 Eval Board have to wait for the computer to respond before sending the data (wouldn't this make the readout much slower?), or will the DRS4 Eval Board keep sending the data to the computer?

With GBit Ethernet you get close to 100 MB/sec, which is the maximal line speed. The protocol to be implemented will achieve that rate. What one usually does is to send events in large blocks upon request from the PC. The trick is to do the request in a clever way, like using a high water mark on the receiving event buffer. So as long as the PC can digest the data quickly enough, the board just keeps sending, which means no overhead.

 

Entry  Mon Apr 23 10:38:51 2012, Guillaume Blanchard, DRS4 Initialization 

Hello,

I am writing a VHDL code to drive a DRS4 chip.

In order to configure the DRS4 chip, I have to set the "Config Register" and the "Write Shift Register" then ... (I do not plan to use simultaneous WR and R so I guess the Write Config Reg. is not needed)

My question is :

When do we have to perform a "Read Shift Register Initialization" ?

Every time before a full read-out, or juste once after a DRS4 reset ?

Further more, is this initialization needed for the ROI mode ?

And at last do the level of the DENABLE and DWRITE signals matter for the "Read Shift Register Initialization" ?

(To sum up : what is the purpose of the Read Shift Register and how does it work ?)

Cordially,

G.Blanchard.

    Reply  Wed Apr 25 13:42:37 2012, Stefan Ritt, DRS4 Initialization 

Guillaume Blanchard wrote:

Hello,

I am writing a VHDL code to drive a DRS4 chip.

In order to configure the DRS4 chip, I have to set the "Config Register" and the "Write Shift Register" then ... (I do not plan to use simultaneous WR and R so I guess the Write Config Reg. is not needed)

My question is :

When do we have to perform a "Read Shift Register Initialization" ?

Every time before a full read-out, or juste once after a DRS4 reset ?

Further more, is this initialization needed for the ROI mode ?

And at last do the level of the DENABLE and DWRITE signals matter for the "Read Shift Register Initialization" ?

(To sum up : what is the purpose of the Read Shift Register and how does it work ?)

Cordially,

G.Blanchard.

There are two readout modes "Full Readout Mode" and  "ROI mode". 

In the Full Readout Mode, the Read Shift Register has to be initialized before the first readout by applying the sequence shown in Figure 11 in the data sheet. This clears the full shift register and sets the first cell to "1". In principle in the following events one applies each time 1024 clocks. Since the shift register is circula, the single "1" rotates through the shift register and is at the same position after 1024 clocks. So in principle the register does not have to be re-initialized. To be hones I have never tried this myself, so I'm not completely sure if that works.

In the ROI mode, you initialize the Read Shift Register by a single RSRLOAD pulse as shown in Figure 15. Since the inverter chain stops at different positions in each event, this pulse has to be applied before each event. The SROUT bits will then tell you where the inverter chain has been stopped.

Most people I know of use the ROI mode, since the initialization is much simpler (just a single pulse).

Best regards,

Stefan

Entry  Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors 

Quick question - what type of connectors are used for the trigger and clock in/out on the v4 eval board?

Entry  Sat Feb 4 11:59:26 2012, Zhongwei Du, what sort of detectors for physical experiment the DRS4 used? 

Hello.

We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the DRS4 can do more accurate than traditional charge integral circuit for charge measuring.

So we need to know what sort of detectors for physical experiment the DRS4 has been used in?

Can you give me some information? For example, Si strip array detector or CsI scintillator r ball detector ? PMT or APD ?

    Reply  Mon Feb 6 08:15:38 2012, Stefan Ritt, what sort of detectors for physical experiment the DRS4 used? 

Zhongwei Du wrote:

Hello.

We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the DRS4 can do more accurate than traditional charge integral circuit for charge measuring.

So we need to know what sort of detectors for physical experiment the DRS4 has been used in?

Can you give me some information? For example, Si strip array detector or CsI scintillator r ball detector ? PMT or APD ?

DRS4 is used for PMTs and APDs. The minimal rise/fall time which can be recorded with the DRS4 on the evaluation boards is about 0.8ns (see elog:84). Concerning charge measurement, it depends on your integration time. If your signal is for example 20ns and you sample with 5 GSPS, you get actually 100 samples. You digitize with 12 bits, but the S/N ratio is more like 11.5 bits. But since you have 100 samples, the accuracy of the measurement scales with sqrt(100)=10. So you have more like 11.5+3 bits = 14-15 bits, or a SNR of 20'000. Now your signal usually does not have an amplitude of 1V, will be more like 100mV or so, in which case your SNR goes to 2000. But this still gives you a resolution of 1/2000 = 0.5 per mille.

We did tests with a Ge detector for spectroscopy applications, where we used a shaping time of 2 micro seconds, both with traditional electronics and the DRS4, integrating the signal over 2 micro seconds. Both gave a resolution of about 0.4%, indicating that the resolution was not limited by the DRS but by the detector.

Best regards,

Stefan 

ELOG V3.1.5-fe60aaf