 Wed Feb 27 13:47:32 2013, Georg Winner, Chip Test - Cell Error
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When starting Chip Test in DRS Command Line Interface, I receive the following message:
Cell error on channel 1, cell 5: -154.4 mV instead 0 mV
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 Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error
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Georg Winner wrote:
When starting Chip Test in DRS Command Line Interface, I receive the following message: |
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Thu Feb 28 10:47:14 2013, Dmitry Hits, clock and trigger outs
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Hi,
I am considering using the DRS4 evaluation board as an ADC card for the wire chamber in the physics lab (VP) experiment at ETH. However, the wire
chamber has 8 outputs, so I would need to have two of such boards. Is it possible to synchronise them, online or offline? From the website, it looks
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Thu Feb 28 12:58:44 2013, Stefan Ritt, clock and trigger outs
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> Hi,
> I am considering using the DRS4 evaluation board as an ADC card for the wire chamber in the physics lab (VP) experiment at ETH. However, the wire
> chamber has 8 outputs, so I would need to have two of such boards. Is it possible to synchronise them, online or offline? From the website, it looks |
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Fri Feb 22 11:46:17 2013, Yury Golod, DRS4 trigger, different polarity
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Normal
0
MicrosoftInternetExplorer4
/* Style Definitions */
table.MsoNormalTable
{mso-style-name:"Обычная |
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Fri Feb 22 11:56:57 2013, Stefan Ritt, DRS4 trigger, different polarity
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Yury Golod wrote:
Normal
0
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Wed Feb 13 16:58:40 2013, Martin Petriska, Nonuniform sampling
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Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly sampled data?
Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga
Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel |
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Wed Feb 13 17:03:53 2013, Stefan Ritt, Nonuniform sampling
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Martin Petriska wrote:
Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly |
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Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors
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Hi Stefan,
A quick question, what is the typical variation of the sampling capacitors in DRS4? Will this variation be significant to affect your sampling
result? |
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Thu Dec 27 09:49:17 2012, Stefan Ritt, variation of sampling capacitors
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Jinhong Wang wrote:
Hi Stefan, |
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Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors
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Stefan Ritt wrote:
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Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors
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Jinhong Wang wrote:
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Tue Feb 5 14:38:35 2013, Stefan Ritt, variation of sampling capacitors
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Jinhong Wang wrote:
Hi Dr. Stefan, |
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Thu Dec 6 09:23:36 2012, Martin Petriska, EVM rev4 board trigger change and drs_example
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I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting for trigger (rev.3 is working). How to do in
drs_exam.cpp for example triggering on Ch0 && CH1 ?
Software 4.0.0, windows version. |
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Fri Dec 14 21:49:29 2012, Stefan Ritt, EVM rev4 board trigger change and drs_example
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Martin Petriska wrote:
I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting |
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Thu Dec 13 12:03:29 2012, Evgeni, DRS-4 trigger
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How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). |
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Thu Dec 13 12:14:35 2012, Stefan Ritt, DRS-4 trigger
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Evgeni wrote:
How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed |
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Thu Dec 13 19:49:47 2012, Evgeni, DRS-4 trigger
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Stefan Ritt wrote:
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Fri Dec 14 08:42:53 2012, Stefan Ritt, DRS-4 trigger 
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Evgeni wrote:
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Fri Dec 14 10:07:54 2012, Evgeni, DRS-4 trigger
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Stefan Ritt wrote:
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Fri Dec 14 10:07:14 2012, Evgeni, DRS-4 trigger
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Evgeni wrote:
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Tue Dec 4 09:24:22 2012, Zhongwei Du, Question of drs4 using
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When Denable and Dwrite is high , the voltage of PLLOUT is 0 V. And the Dtap is turn high with no delay when the Denable turns high.
After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs
changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first |
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Tue Dec 4 09:39:44 2012, Stefan Ritt, Question of drs4 using
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Zhongwei Du wrote:
When Denable and Dwrite is high , the voltage of PLLOUT is 0 V. And the Dtap is turn high |
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Tue Dec 4 09:50:11 2012, Zhongwei Du, Question of drs4 using
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Stefan Ritt wrote:
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Tue Dec 4 09:55:43 2012, Stefan Ritt, Question of drs4 using
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Zhongwei Du wrote:
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Mon Dec 3 08:32:28 2012, Gyuhee Kim, Another question about using multi boards.
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Hi.
I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!) |
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Mon Dec 3 09:18:09 2012, Stefan Ritt, Another question about using multi boards.
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Gyuhee Kim wrote:
Hi. |
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Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards.
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Stefan Ritt wrote:
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Wed Nov 28 16:54:46 2012, Stefan Ritt, DRS Oscilloscope for Raspberry Pi and Mac OSX 10.8
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I made a pre-compiled package for Mac OSX 10.8 (Mountain Lion), so one should be able to install the DRS Oscilloscope software with one mouse click on
a recent Mac.
The Makefile in the tar ball now also supports OSX 10.8, so one could even compile it from the sources on a Mac, after libusb-1.0 and wxWidgets |
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Wed Nov 21 08:34:52 2012, Gyuhee Kim, Question for using Multi board
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Hi.
I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ. |
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Wed Nov 21 08:38:26 2012, Stefan Ritt, Question for using Multi board
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Gyuhee Kim wrote:
Hi. |
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Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board
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Stefan Ritt wrote:
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Mon Oct 29 18:30:28 2012, Martin Petriska, GetWave
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I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) etc...is used. Is there primary (cell) calibration,
secondary calibration (Readout) and remove Spikes used, as in DRS Oscilloscope application? |
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Tue Nov 13 11:26:32 2012, Stefan Ritt, GetWave
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Martin Petriska wrote:
I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) |
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Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware
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Hi,
We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I
look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto |
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Thu Nov 1 20:17:42 2012, Stefan Ritt, DRS4 firmware
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hongwei yang wrote:
Hi, |
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Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware
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hongwei yang wrote:
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Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware
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hongwei yang wrote:
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Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Fri Oct 12 14:06:04 2012, Moritz von Witzleben, DRS abbreviation
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Hello,
what is the abbreviation of DRS?
Thanks and kind Regards, |
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Fri Oct 12 14:09:37 2012, Stefan Ritt, DRS abbreviation
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Moritz von Witzleben wrote:
Hello, |
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Thu Oct 4 20:50:36 2012, Zach Miller, DRS5
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Hi,
Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input
channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release |
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Thu Oct 4 20:59:18 2012, Stefan Ritt, DRS5
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Zach Miller wrote:
Hi, |
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Thu Oct 4 21:07:27 2012, Zach Miller, DRS5
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Stefan Ritt wrote:
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Tue Aug 28 17:52:45 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
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Hi,
I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt
to build the drs-4.0.0, I get this similar error: |
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Wed Aug 29 10:52:44 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp
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Zach Miller wrote:
Hi, |
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Wed Aug 29 16:42:42 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
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Stefan Ritt wrote:
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Wed Aug 29 16:45:36 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp
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Zach Miller wrote:
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Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
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Stefan Ritt wrote:
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Wed Aug 1 17:42:32 2012, Mayank S. Rajguru, Calculation of loop filter parameters (R,C1and C1) for 1 GHz
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Hi,
we are planning to use the DRS4 in our board for 1 GHz sampling and digitization.
I have seen in the data sheet that "For the PLL to work, an external loop filter is required. This filter ensures quick locking and stable |
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Mon Aug 6 02:44:00 2012, Stefan Ritt, Calculation of loop filter parameters (R,C1and C1) for 1 GHz
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Mayank S. Rajguru wrote:
Hi, |
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Mon Jul 9 14:14:48 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows
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Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++
with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions
will be helpful. Thank you. |
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Tue Jul 10 13:15:00 2012, Stefan Ritt, Problem compiling drs_exam.cpp on windows
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Ivan Petrov wrote:
Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to |
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Wed Jul 11 10:04:51 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows
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Stefan Ritt wrote:
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Tue Mar 20 16:23:33 2012, Martin Petriska, triger for measuring time between pulses in channels
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I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is
version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger
on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold |
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Tue Mar 20 16:33:50 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Martin Petriska wrote:
I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger |
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Wed Mar 21 09:33:00 2012, Martin Petriska, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
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Wed Mar 21 09:39:33 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Martin Petriska wrote:
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Wed Jun 20 10:40:21 2012, Ivan Petrov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
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Wed Jun 20 12:45:05 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Ivan Petrov wrote:
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Wed Jun 20 14:36:01 2012, Ivan Petrov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
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Wed Jun 20 14:44:38 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Ivan Petrov wrote:
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Sat Jun 23 00:29:52 2012, Andrey Kuznetsov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
On the evaluation board, yes. This board is not optimized for high readout rate. If you do your own |
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Mon Jun 25 14:21:13 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Andrey Kuznetsov wrote:
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Mon Apr 23 10:38:51 2012, Guillaume Blanchard, DRS4 Initialization
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Hello,
I am writing a VHDL code to drive a DRS4 chip.
In order to configure the DRS4 chip, I have to set the "Config Register" and the "Write Shift Register" then ... (I do not |
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Wed Apr 25 13:42:37 2012, Stefan Ritt, DRS4 Initialization
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Guillaume Blanchard wrote:
Hello, |