Tue May 26 11:10:27 2020, xggg, Domino wave
|
Hi Stefan,
According to the datasheet DRS_rev09, the write signal is always 16 cells wide. So when the domino wave runs in infinite mode and be stopped
by setting DENABLE low , there are always 16 cells capicitors tracking the input signal . It means that the effective sample cells is 1024-16=1008? That's |
Sun May 26 13:08:52 2013, tmiron alon,
|
Hallo,
I'm using DRS4 Evaluation Board Rev 4.0 and I'm trying to change the output of the samples to be an average of # measurements (1000
or even more) |
Fri Jun 7 11:44:17 2013, tmiron alon, thank you
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Stefan Ritt wrote:
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Mon Jun 10 14:09:13 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Thu Jul 4 08:32:11 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Thu Jul 4 09:07:24 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Thu Jul 4 10:01:06 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Tue Jul 16 10:02:28 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Sun Jul 28 09:52:25 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Mon Aug 12 15:08:17 2013, tmiron alon, add an average ability to the Scope
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Stefan Ritt wrote:
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Sat Jan 15 09:13:42 2022, student_riku, I want to know about the readout
|
Hello, everyone.
I'm a student in Japan.
Please forgive me if this is a very rudimentary question. |
Wed Jan 26 06:44:11 2022, student_riku, I want to know about the readout
|
Dear Stefan
Thanks a lot.
I solved it. |
Wed Feb 22 11:36:51 2012, sonal, DRS4- analog pulse counting
|
Hello Sir,
Regarding to analog pulse counting by using DRS4 Rev.2.0 board, |
Wed Nov 30 17:48:39 2016, samridha kunwar, DRS4 Initiation
|
I am having a general problem getting read back using the ROI mode. In the transparent mode everything looks good. These are the steps that I take:
1) configure register (b"11111111",addr = "1100")
2) configure write shift register (b"11111111", addr = "1101") |
Fri Dec 2 15:32:52 2016, samridha kunwar, DRS4 Initiation
|
Thanks for replying Stefan.
I was more so just concerned with the steps in the firmware when I had asked. However, yes the ROFS (1.05V) and O-OFS (0.9 V was 1.3 V earlier
but, changed this becasue of ADC input requirements) are per spec, the VDD voltages are all there and input voltages are within the rails and finally the |
Wed Feb 10 02:57:55 2010, pepe sanchez lopez, Hello
|
hello i am an student and i want to do my final project with drs4 board and i really can´t find how to open waveform file and how can i save or
opened many of them quickly.
if you can tell me how i will be very grateful. |
Wed Dec 23 15:38:14 2015, mony orbach, Dtap stops toggling after 40msec
|
Hi
the drs4 start to generate Dtap signal after reset and standard configuration.
while in reset Denable and Dwrite are low |
Thu Dec 24 10:51:31 2015, mony orbach, Dtap stops toggling after 40msec
|
my refclk is 1.25Mhz
what are the inputs and voltage you need to see?
Avdd and Dvdd are 2.5v |
Sun Dec 27 15:06:59 2015, mony orbach, Dtap stops toggling after 40msec
|
Hi
We have some meesurs to show (attached)
Dtap and Denable
Dtap+Denable in zoom
Dtap + Ref+
Dtap + Dspeed
From the screen shots |
Sun Dec 27 15:41:32 2015, mony orbach, Dtap stops toggling after 40msec
|
Hi
We have some measures to show (attached)
Dtap and Denable
Dtap+Denable in zoom
Dtap + Refck+
Dtap + Dspeed
From the screen |
Mon Dec 28 11:21:54 2015, mony orbach, Dtap stops toggling after 40msec
|
Hi Stefan
Thanks for your input.
We are in the process of assemble another PCB board. |
Wed Dec 30 16:25:35 2015, mony orbach, Dtap stops toggling after 40msec
|
Hi
We have resolve the problem, the Dtap is now working correctly.
There were two problems: |
Thu Jan 14 14:00:26 2016, mony orbach, Dtap stops toggling after 40msec
|
surrey i forgot to update..
after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111
after making shore that a0-a3 never get 1111 value thae drs4 woks as expected. |
Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter
|
Hi all
|
Tue Aug 27 16:14:49 2013, lengchongyang,
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Hello everyone!I'm a new user of DRS4 board,but it seems that some files are missing
in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!
T |
Wed Aug 28 04:05:48 2013, lengchongyang,
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lengchongyang wrote:
Hello everyone!I'm a new user of DRS4 |
Tue Dec 10 14:48:42 2013, ismail okan atakisi, measurement range
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I m trying to measure lifetime in our lab and I intend to take
measurement with DRS4 at that point I have a little bit confused about
DRS4 time range.In My system I opened 10 us gate but after triggering |
Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware
|
Hi,
We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I
look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto |
Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware
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hongwei yang wrote:
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Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Fri Aug 7 18:41:37 2015, dante, DRS4
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Hi
I have just installed DRS4, but when I try to view it from the USB it don't work. Why?
|
Tue Aug 27 08:33:22 2019, chinmay basu, DRS4
|
Is DRS4 suitable for use with Silicon surface barrier detectors? |
Wed Nov 22 08:31:03 2017, chen wenjun , using of the DRS Command Line Interface
|
Hello! I'm using DRS4 evaluation board V5 with the drs command line interface,but the mannal only explained the meaning of the command--"info".And
I can't get the hang of the use of other commands through "help",so is there anywhere can I learn more about other commands?Or I can only
learn it through the datasheet of DRS4 chip. |
Wed Nov 22 08:58:33 2017, chen wenjun , using of the DRS Command Line Interface
|
OK!Thank you! One more question,when I use the Oscillocope ,I found that the actual speed is a constant value of 1.007G,how can change this speed.
Stefan
Ritt wrote:
The command line interface is more a debugging tool for experts, and |
Wed Nov 22 09:19:11 2017, chen wenjun , using of the DRS Command Line Interface
|
Thank you very much !! All my fault for I thought it too comlicated. Thank you sincerely!
Stefan
Ritt wrote:
Remove the check mark from the "Lock" box and enter a different |
Thu Jan 25 05:24:05 2018, chen wenjun, problem with the drscl(drs507)
|
Hi! Stefan:
when I change a new computer(win7,64bit),I meet a problem that the drscl app cannot found the board! It shows"USB successfully scanned,but
no boards found",but the drsosc runs well . when I connect to other win7*64bits computer,only one of them runs property! Is there any driver else |
Thu Jan 25 06:10:52 2018, chen wenjun, drscl doesn't find eval board but drsosc does (Windows 7)
|
Hi! Jim:
It seems that I meet the same question with you ,and I am confused ,have you find out the reason about this problem?Or can you tell me
how you deal with it? |
Thu Jan 25 08:07:32 2018, chen wenjun, problem with the drscl(drs507)
|
I have tried about 4 computers,only one worked fine.I truly want to know how others get this fixed,can you get in touch with them?
Stefan
Ritt wrote:
This problem has been reported by several people, like |
Wed Mar 14 09:13:39 2018, chen wenjun, confusion about the description in drs.cpp
|
Hi,Stefan:
recently,whtn I study the drs.cpp code ,I found that the buffer[1] is char but the addr and the base_addr are all unsigned int,isn't
there any problem that the addr may be cut off to 8 bits? Also ,I found that the data fpga recieved from the usb is 16 bits,so how can fpga get the true |
Sun May 6 08:13:37 2018, chen wenjun, confusion about the description in drs.cpp
|
Hi Stefan:
I'm still confused that althought the 8 bits buffer is enough,the FPGA receive the command through the uc_data_i register which is
16 bits wides.As we can see in the firmware, the locbus_addr is 32 bits wides. Does it means the locbus_addr[31:8] are always '0' because the address |
Mon Aug 29 09:36:34 2016, benjamin legeyt, increment write config register on the fly?
|
Hello,
I have a question about using the write config register to enable/disable sampling on the fly. I am looking to instrument an experiment
at EPFL where multiple short events need to be captured during a 20us period followed by an 80us quiet period during which we could read out the chip. |
Mon Aug 29 12:18:49 2016, benjamin legeyt, increment write config register on the fly?
|
If I may trouble you for a little more information, the critical point then is that there should not be any zeroes in the write config register
while the sampling is active? In case it was unclear I would only be reading out once sampling was stopped (dwrite = 0).
As for the readout, I know that I would have to read out all 1024 samples each time, and keep track of where each channel stopped in the FPGA. |
Tue Jul 23 22:31:08 2013, alonzi, Evaluation Board Behavior
|
Working with the DRS evaluation board we noticed some funny behavior: See attatchment 1. In about 1% of scope traces we see the first and last bin take
on a value substantially different from the baseline, note the small spikes on the end of the traces. These spikes occur across all channels and either
appear in all channels or in none. Attachment two shows what several thousand scope traces look like. You can clearly see that some of the traces are offset |
Tue Jul 23 22:42:31 2013, alonzi, Evaluation Board Behavior
|
Stefan Ritt wrote:
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Wed Dec 30 14:28:33 2009, aliyilmaz, normal_mode_in_drs_exam.cpp
|
Dear Mr. S. Ritt
i am Ms. student , am working with your DRS4 board to calculate the time of flight of the cosmic particle which passes
trough the hodoscope . i see the signals at scope , which is negative (i don't want to take positive side of the signal). |
Mon Oct 31 09:15:02 2011, Zhongwei Du, How to link PMT
|
I want to measure the signal from PMT . But it is a current signal, should i just put a series resistance, or use a amplifier to convert it to voltage
signal before drs4?
Can you give me some advice ? |
Sat Feb 4 11:59:26 2012, Zhongwei Du, what sort of detectors for physical experiment the DRS4 used?
|
Hello.
We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the
DRS4 can do more accurate than traditional charge integral circuit for charge measuring. |
Tue Dec 4 09:24:22 2012, Zhongwei Du, Question of drs4 using
|
When Denable and Dwrite is high , the voltage of PLLOUT is 0 V. And the Dtap is turn high with no delay when the Denable turns high.
After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs
changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first |
Tue Dec 4 09:50:11 2012, Zhongwei Du, Question of drs4 using
|
Stefan Ritt wrote:
|
Tue Aug 28 17:52:45 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
|
Hi,
I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt
to build the drs-4.0.0, I get this similar error: |
Wed Aug 29 16:42:42 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
|
Stefan Ritt wrote:
|
Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
|
Stefan Ritt wrote:
|
Thu Oct 4 20:50:36 2012, Zach Miller, DRS5
|
Hi,
Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input
channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release |
Thu Oct 4 21:07:27 2012, Zach Miller, DRS5
|
Stefan Ritt wrote:
|
Mon Jul 14 19:03:05 2014, Yves Bianga, change cascading from 1024 to 2048 bins for each input channel
|
Hello,
I want to ask whether it is possible to modify a Evaluation Board 5.0 from 1024 to 2048 cells for each of the 4 input channels.
On
the rev50 manual at page 31 I found an option to connect the 4 unused channels by setting 8 solder bridges.
The source code for controlling |
Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support
|
Hi i am using DRS4 Eval Board V2, How to acquire data to a bin file using it. |
Fri Feb 22 11:46:17 2013, Yury Golod, DRS4 trigger, different polarity
|
Normal
0
MicrosoftInternetExplorer4
/* Style Definitions */
table.MsoNormalTable
{mso-style-name:"Обычная |
Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors
|
Quick question - what type of connectors are used for the trigger and clock in/out on the v4 eval board? |
Thu May 12 05:18:47 2016, Yu, Problem For Software Download
|
Hi
I can't download the software for windows on this website 'www.psi.ch/drs/software-download', there is some mistake when i
click on download. |
Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing
|
Hi,
I'm running a LIDAR application that requires that every outgoing pulse be captured. My current setup firess sets of 20-50 pulses at
1 ms intervals, about 10 times a second, but only 10-20 pulses a second are captured. |
Wed Dec 20 15:30:38 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Hi,
I'm trying to do the same thing (get 1 channel with 8192 bins), but I'm having some trouble with it. When I call SetChannelConfig(0,
8, 1) as suggeted, I get output that looks like noise on all readouts. Could you please explain what is supposed to happen in this case? |
Wed Dec 20 16:30:45 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Hi,
The board is modified (and checks out with the DRSScope program). Could you please point me to the drs_exam_2048.cpp file? I can't seem to
fine the most up-to-date git repository.... |
Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width
|
I am using a DRS4 Evaluation Board v5 and running the drsosc.exe version 5.06 on a Window 7 machine. I have performed the voltage and timing calibration.
With test pulses on channel 1 and 2, I collected binary data file with all 4 channels active sampling at 5GSPS.
Attached is a distribution of the bin_width vs. cell # for all the 4 channels. Note that there are few cells with bin_width < 10 ps. |
Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing
|
Using a test pulse split into two channels of the DRS4 Evaluation Board v5, I looked at the time resolution using a leading edge threshold.
The voltage and timing calibration was performed. One method (1) is to linearly interpolate between two points of the raw waveform that
is above and below the threshold (this is exactly the algorithm given in read_binary.c in the drs4 source distribution); and another (2) is to |
Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing
|
Just a follow-up update.
It turns out that I was using a cubic spline interpolation with smoothing. If I required the cubic spline to go through the sampled points, then
I obtained similar time resolution as the simple linear interpolation. |
Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs
|
Hi all,
When connecting the board and running the Zadig program, some Windows PCs may return "driver installation failed." I coudn't
find the solution from their download website. So I started the drscl first. Apparently it shows: Successfully scanned, but |
Tue Nov 3 22:37:56 2015, Will Flanagan, Latest macro for DRS4 V5
|
Hi DRS4 Experts,
I have an extremely naive question: Is there any official macro to unpack the DRS4 binary files? All I am looking to do is to plot a few of my
waveforms and manipulate them in root. I am using OSX 10.10 and ROOT 5.34. |
Tue Nov 3 23:15:38 2015, Will Flanagan, Latest macro for DRS4 V5
|
I should of course mention that I looked through the DRS4 website and didn't see anything obvious: https://www.psi.ch/drs/evaluation-board
Thanks,
Will |
Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5
|
Hi Stefan,
This is absolutely perfect.
Thanks, |
Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform
|
Hi DRS4 Experts,
I have been analyzing DRS4 binary data with scripts based on Stefan's (very helpful!) macro:
https://midas.psi.ch/elogs/DRS4+Forum/361 |
Thu Oct 6 15:23:18 2016, Will Flanagan,
|
Hi Stefan,
That is exactly what I'm looking for. Thanks again!
Will |
Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps?
|
Dear DRS4 community,
Is there a way to extract timestamps with sub-ms precision? The milliseconds of an event is clearly given when unpacking the header. I would
like to determine how far apart events are when they are within the same millisecond. |
Wed Apr 16 03:22:43 2014, Wang , why is the first channel output error?
|
Hi,
|
Thu Apr 17 12:02:28 2014, Wang , The first channel is wrong.
|
Hi,
I want to describe this phenomenon again. The diagram |
Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10
|
Dear Laura
You need to disable driver signature enforcement. Then try again with path option.
It helped me. |
Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output
|
Hello Stefan
I tried to convert binary to a simple txt file and found next problem - strange time output.
Here is output from little modification for read_binary.cpp (Its last output line also is strange: dT = -1.#IOns +- -1.$ps) |
Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output
|
Hi again.
Okay, it works with 5.05 version very good and it is enough for me.
Besides, |
Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset
|
Hello.
I have a simple question, can I set SetTriggerDelayNs() more than 1631 ns? |
Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset
|
Thank you for your reply!
Stefan
Ritt wrote:
No this is not possible. But you can delay your signal externally (like |
Tue Jan 31 01:37:35 2017, VO HONG HAI, LLD and ULD discriminations,
|
Dear Stefan,
Is there any way to develop LLD and ULD discrimination in DSR-4 evaluation board?
Best regards,
V.H.Hai |
Wed Jul 30 11:38:58 2014, Tsutomu Nagayoshi, Sampling speed of DRS4 Board ver4
|
Hello!
I have a question concerning the sampling speed of the DRS4 evaluation board.
It is written in the manual that the sampling speed of DRS4 Evaluation Board is supported above 0.7 GHz. |
Wed Jan 17 09:51:16 2018, Tran Cong Thien, The input signals recorded are different with the signal showed in oscilloscope
|
Dear Stefan,
I am using an DRS4 board to record the signals from an plastic scintillator detector. It was working really good, yet a few day ago the signals
became "not right". When I checked the signal using an oscilloscope it show the normal signals previously recorded. The signal amplitude |
Thu May 29 04:22:43 2014, Toshihiro Nonaka, CalibrationWaveform
|
I'm writing the drs_exam.cpp to use multi-boards(v3, firmware:4.0.0), and taking data succeeded. But I have several questions about function written
in DRS.cpp.
|
Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem
|
Dear all,
I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.
Recently however, I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board. |
Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem
|
The serial number has been fixed by using drscl. Thank you!
Stefan
Ritt wrote:
If dis- and reconnecting the board does not help, there is the (small) |
Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards
|
Hello,
I 'm using four evaluation boards v.3 to construct the multi-board DAQ system. One channel for each board is used as reference clock, then
calibrate timing offline, which allow below 10ps resolution between boards. |
Fri Feb 26 17:05:26 2021, Tom Schneider, Trouble getting PLL to lock
|
Hello,
I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock. I'm feeding CLKIN with a 1MHz CMOS clock
(REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board. I see from the datasheet that the PLL is enabled by default, |
Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock
|
Stefan,
Thanks for responding so quickly. Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic). BIAS is
0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the |
Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock
|
Probe capacitance makes that tricky - if I put my probe on DSPEED, I see that it starts at approx. 2.5V then gradually decreases until it hits 0V.
DTAP decreases from 3MHz to 0 during this time.
I'll try to get something together to show you. |
Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock
|
Thats not a simple modification to my PCB, but I'll give it a try. Thanks for your help
Stefan
Ritt wrote:
Sounds to me like your REFCLK is not getting through or your PLL loop |
Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock
|
I found the problem, and it had nothing to do with the CMOS clock input. As it turns out, even though I was using the default state of the config
register, I still had to write to it after powerup. Once I did that, the PLL locked immediately.
-Tom |
Tue Jan 25 14:15:00 2022, Thomas M., Regarding measuring for a set time
|
Hello,
I'm working on a project wherein we're looking at photomultipliers. We've already acquired a DRS4 evaluation board with the intent
of using it to gather our data. |
Tue Jan 25 14:44:49 2022, Thomas M., Regarding measuring for a set time
|
Yes, you've got it exactly right. Thank you, that helps a lot!
Thomas
Stefan |
Fri Feb 24 17:34:28 2017, Tarik Zengin, Passing parameters to drscl
|
Hi everyone,
I wonder if there is a way to pass parameters to drscl. What I specifically want to do is calling drscl from a shell script and read/save some
data. I want to schedule a measurement. Therefore I need to call drscl from the command line using some parameters. |
Wed Jan 20 12:14:49 2021, Taegyu Lee, drs4 persistence
|
Dear all,
I have a question about the function that drs4 can perform.
Is there any function in drs4 that is analogous to that of "persistence display" in oscilloscope?? (accumulating pulses) |
Sat Apr 15 03:48:31 2017, Strahinja Lukic, Wave rotation during transfer from the board?
|
I don't know if this question is already documented elsewhere.
I am developing a DAQ code for the DRS evaluation board, v4 for a test beam experiment. I link parts of the existing DRS code as a library.
To understand the effect of various flags used in calls to the functions DRSBoard::GetTime() and DRSBoard::GetWave(), I performed several tests |
Thu Apr 20 06:30:13 2017, Strahinja Lukic, Wave rotation during transfer from the board?
|
Thanks.
Strahinja
Stefan |
Tue Feb 27 13:17:00 2018, Steven Block, WIndows Connection problem with drs507 SOLVED
|
Hello All,
I too have been struggling with trying to get the drs4 (507) to work on my windows machine and I found it to be a problem with the libusb library.
My solution is as follows and has worked on multiple PC's. I ran this solution after I first plugged in the drs4 and installed 507. |
Tue Feb 27 16:34:26 2018, Steven Block, DRS4 Dead times 6x
|
Hello All,
I am currently trying to figure out how to properly characterize the dead time of the DRS4 board. My most recent experiment to try and answer
this question involved using an external trigger that can range from 1Hz to 2MHz. I fed this trigger into the DRS4 and collected 1000 samples with no input |
Tue Feb 27 18:04:18 2018, Steven Block, DRS4 Dead times
|
That is extremely helpful! Many thanks. One more question; If I were to take inputs from 2 channels at once, would that scale the dead time to 64us
using your example?
Steven |
Fri Mar 2 18:08:55 2018, Steven Block, ROI
|
Hello,
I have a question about how ROI works. From what I have read, it will only save data that ocurs some time |
Fri Mar 2 21:05:48 2018, Steven Block, ROI
|
Great! That is very helpful.
One more question. If no signals were detected in the 1024*200ps time frame in ROI mode, would the DRS4 go dead for 32us (or 30us depending on
the supply) for, or would it dump the earliest events in the buffer for the more recent ones until it detects a signal to readout? Or rather, does |
Mon Oct 21 14:43:21 2013, Stephane Debieux, DRS4 analog outputs - interfacing DRS4 to AD9222 ADC
|
Hi,
I wish to interface the DRS4 with the 8-channel ADC AD9222 (or AD9637).
I'm reading from the DRS4 datasheet that "the analog output of the DRS4 chip has been designed to match directly the input of the AD9222". |
Tue Oct 7 14:09:02 2014, Stephane Debieux, USB Microcontroller firmware
|
Hi,
I'm trying to recompile the USB microcontroller firmware starting from the drs_eval.c file but I'm not able to get a .iic file close to the one
provided with the eval board. It seems to me that this drs_eval.iic file does not match the drs_eval.c and drs_eval.hex files or that I'm doing something |
Mon Oct 13 17:08:40 2014, Stephane Debieux, USB Microcontroller firmware
|
Stefan Ritt wrote:
|
Tue Oct 14 16:21:07 2014, Stephane Debieux, USB Microcontroller firmware
|
Stefan Ritt wrote:
|
Tue Oct 14 16:34:45 2014, Stephane Debieux, USB Microcontroller firmware
|
Stefan Ritt wrote:
|
Tue Oct 14 16:51:37 2014, Stephane Debieux, USB Microcontroller firmware
|
Stefan Ritt wrote:
|
Mon Dec 15 13:37:38 2008, Stefan Ritt, Welcome
|
Welcome to the DRS4 Discussion Forum. This forum contains information and discussions related to the DRS4 chip. Please subscribe to this forum
to receive automatic email updates. If you have any technical questions, please feel free to post it here. |
Wed Jan 14 12:02:04 2009, Stefan Ritt, External Trigger Input requirements
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Several people mentioned that the external trigger input (TTL) does not work on the DRS4 Evaluation Board Rev. 1.1. This is not true. The requirement
however is that the input signal must exceed approximately 1.8V. Since the input is terminated with 50 Ohms, not all TTL drivers may deliver enough current
to exceed this threshold. To verify this, the trigger signal can be monitored with an oscilloscope at test point J24. Only if the input signal exceeds |
Wed Jan 14 13:41:44 2009, Stefan Ritt, External Trigger Input requirements
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Another tricky issue comes from the fact that the external TTL trigger and the comparator are in a logical OR. So if the comparator level is set
such that the signal is always over the threshold, the trigger is always "on" and the TTL trigger does not have any effect. It is therefore necessary |
Wed Feb 11 12:21:07 2009, Stefan Ritt, Corrected datasheet Rev. 0.8
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Please note the new datasheet Rev. 0.8 available from the DRS web site. It fixes the label of pin #76, which was AGND but is actualy AVDD. The
input IN8+ is located at pin #20 and not at pin #19 as described in the old table 2. |
Mon Feb 23 09:24:24 2009, Stefan Ritt, Rise-time measurements
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Many applications using the DRS4 need to measure fast rising signals, like for PMTs or MCPs. This short note shows the minimal rise-times which can be
measured with different input signal conditioning.
Evaluation Board
The evaluation board contains four passive transformers ADT1-1WT from Mini-Circuits to convert the single-ended input |
Mon Apr 27 15:09:49 2009, Stefan Ritt, Amplitude and Timing calibration for DRS4 Evaluation Board
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This is a quick notification to all users of the current DRS4 evaluation board.
As you all know, the DRS4 chip needs some calibration for each individual cell which corrects the offset and the non-equidistant width in time.
While the first evaluation boards have been shipped without this calibration, the current version of the software implements a full amplitude and timing |
Tue Apr 28 11:44:07 2009, Stefan Ritt, Simple example application to read a DRS evaluation board
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Several people asked for s simple application to guide them in writing their own application to read out a DRS board. Such an application has been added
in software revions 2.1.1 and is attached to this message. This example program drs_exam.cpp written
in C++ does the following necessary steps to access a DRS board: |
Wed Apr 29 07:57:33 2009, Stefan Ritt, Simple example application to read a DRS evaluation board
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Stefan Ritt wrote:
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Wed Jun 10 12:46:43 2009, Stefan Ritt, Input range switch added in Version 2.1.3
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A new software verison for the DRS4 Evaluation Board has been has been released. Version 2.1.3 adds a switch for the input range of the DRS4 board.
Once can choose between -0.5V...0.5V and 0V...1V:
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Tue Jul 7 16:39:57 2009, Stefan Ritt, Power up problem and remedy
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Maybe some of you have experienced that the DRS4 chip can get pretty hot after power up. After it's initialized the first time, the power consumption
goes back to normal. I finally found the cause of this problem and have a remedy. Here is the new paragraph from the updated data sheet:
During power-up, care has to be taken that the DENABLE and DWRITE signals are low. If not, the domino wave can get started before the power |
Thu Jul 9 09:11:03 2009, Stefan Ritt, Current problems with drs_exam.cpp
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The current version of the DRS readout example program drs_exam.cpp has two problems:
The sampling frequency cannot be changed, it will always stay in the region around 5 GSPS
The waveform obtained by GetWave
is rotated such that the first DRS cell corresponds to the first array bin
Both problems have been fixed and the fix will be contained |
Tue Oct 6 11:20:39 2009, Stefan Ritt, VDD instability
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It has turned out that the stability of the AVDD and DVDD power supplies for the DRS4 are very critical. On the evaluation board I use a REG1117-2.5,
on our VME board I use a ADP3338-2.5 for the DVDD power supply. When the domino wave is started, the power consumption of the DRS4 chip jumps up by ~40
mA, which has to be compensated by the linear regulator. Following screen shot shows what happens: |
Wed Oct 7 17:58:20 2009, Stefan Ritt, VDD switch off speed
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It turned out that the VDD switch off speed plays some important role. On our VME board, we have a linear regulator, then a 4.7 uF capacitor, then the
DRS4 chip (DVDD and AVDD). When switching off the VME power, it takes quite some time to discharge the 4.7 uF capacitor, since the DRS4 chip goes into
a high impedance mode if VDD < ~1V. This gives following VDD trace: |
Fri Oct 16 10:16:10 2009, Stefan Ritt, DSR4 Full Readout Mode
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Jinhong Wang wrote:
Hello Mr. Stefan Ritt |
Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4
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Jinhong Wang wrote:
Dear Mr. Stefan Ritt. |
Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4
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Jinhong Wang wrote:
Does it mean that this buffer shifts a voltage of about 1.3V for the primary differential range?
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Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4
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Jinhong Wang wrote:
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Tue Dec 15 14:38:09 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
Dear Mr. S. Ritt |
Mon Dec 21 16:52:08 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
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Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
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Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp
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aliyilmaz wrote:
Dear Mr. S. Ritt |
Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM
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Hao Huan wrote:
Hi Stefan, |
Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello
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pepe sanchez lopez wrote:
hello i am an student and i want to do my final project with drs4 board and i really can´t find |
Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output
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Ron Grazioso wrote:
It looks like the pulse is there but there is something corrupting the data only in binary form. |
Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
Hi Stefan, |
Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010
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Hello,
may I draw your attention to the upcoming Real Time Conference 2010, taking place in Lisbon, Portugal, May 23rd to May 28th, 2010.
http://rt2010.ipfn.ist.utl.pt/ |
Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN |
Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit
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Hao Huan wrote:
Hi Stefan, |
Wed Mar 10 10:07:28 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip
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Hao Huan wrote:
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation |
Thu Mar 11 11:45:52 2010, Stefan Ritt, Readout of DRS Data
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Hao Huan wrote:
Hi Stefan, |
Fri Mar 12 08:04:44 2010, Stefan Ritt, Input Bandwidth of the DRS Chip
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Hao Huan wrote:
I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth |
Thu Mar 18 22:10:41 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip
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Hao Huan wrote:
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Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration
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Hao Huan wrote:
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. |
Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter
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lorenzo neri wrote:
Hi all |
Tue Apr 13 13:56:07 2010, Stefan Ritt, Baseline Variation In Data
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Hao Huan wrote:
Hi Stefan, |
Tue Apr 13 14:15:16 2010, Stefan Ritt, Simple example application to read a DRS evaluation board
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Heejong Kim wrote:
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Wed Apr 14 16:34:28 2010, Stefan Ritt, version 1.2 evaluation board with firmware 13279?
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Heejong Kim wrote:
Hi, Stefan,
I found that my collaborator bought 2 older version of evaluation board before.
They |
Thu Apr 15 13:48:40 2010, Stefan Ritt, ROFS Configuration
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Hao Huan wrote:
Hi Stefan, |
Mon May 3 11:09:12 2010, Stefan Ritt, DRS4 chip model
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Ignacio Diéguez Estremera wrote:
Hi all, |
Mon May 3 17:10:29 2010, Stefan Ritt, DRS4 chip model
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Ignacio Diéguez Estremera wrote:
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Tue May 4 11:26:21 2010, Stefan Ritt, DRS4 chip model
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Ignacio Diéguez Estremera wrote:
So i guess i won't be able to include drs4 in my simulations :-(. Any other |
Thu May 6 08:15:39 2010, Stefan Ritt, Random noise spec in datasheet
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Ignacio Diéguez Estremera wrote:
Hi, |
Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model
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Jinhong Wang wrote:
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Fri May 14 08:40:14 2010, Stefan Ritt, DVDD Problem of DRS 4
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Hao Huan wrote:
Hi Stefan, |
Tue May 18 08:23:07 2010, Stefan Ritt, DVDD Problem of DRS 4
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Hao Huan wrote:
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Tue May 18 09:24:02 2010, Stefan Ritt, Reference design for DRS4 active input buffer
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The design of high frequency differential input stages with the DRS4 is a challenge, since the chip draws quite some current at the input (up to 1 mA
at 5 GSPS), which must be sourced by the input buffer. A simple transformer as used in the DRS4 Evaluation Board 2.0 limits the bandwidth to 220 MHz. In
meantime two active input stages have been worked out and successfully been tested, both utilizing the THS4508 differential amplifier. The first design |
Wed May 19 09:16:02 2010, Stefan Ritt, DVDD Problem of DRS 4
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Hao Huan wrote:
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Tue Jun 1 13:36:18 2010, Stefan Ritt, High Frequency Input for DRS
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Hao Huan wrote:
Hi Stefan, |
Fri Jun 18 11:45:18 2010, Stefan Ritt, DVDD Problem of DRS 4
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Jinhong Wang wrote:
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Tue Jun 22 11:02:30 2010, Stefan Ritt, Reset of DRS4
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Jinhong Wang wrote:
Hi Stefan, |
Tue Jun 22 11:35:18 2010, Stefan Ritt, Reset of DRS4
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Jinhong Wang wrote:
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Mon Jul 12 16:07:37 2010, Stefan Ritt, Announcement evaluation board V3
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Dear DRS4 users,
a new version of the evaluation board has been designed and is in production now. The main difference is that it uses active input amplifiers,
which result in an analog bandwidth of 700 MHz (as compared with the 220 MHz of the previous board) at moderate power consumption, so the board can still |
Mon Jul 19 12:47:17 2010, Stefan Ritt, Fixed Patter Timing Jitter
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Jinhong Wang wrote:
Hi Stefan, can you give some suggestions on determination of fixed pattern timing jitter of DRS4? |
Wed Jul 21 10:58:20 2010, Stefan Ritt, ENOB of DRS
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Jinhong Wang wrote:
Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip |
Tue Nov 16 16:38:06 2010, Stefan Ritt, Reference design for DRS4 active input buffer
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Jinhong Wang wrote:
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Sat Feb 19 22:46:35 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards
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S S Upadhya wrote:
Dear sir, |
Mon Feb 21 08:10:31 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards
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Stefan Ritt wrote:
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Fri Feb 25 10:13:51 2011, Stefan Ritt, Announcement digital pulse processing workshop
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Dear colleague,
if you live not so far from Zurich, you might be interested in this workshop:
http://www.xtronix.ch/hep/psi_workshop.htm |
Fri Apr 15 08:28:54 2011, Stefan Ritt, Fixes to DOScreen.cpp for recent built on linux
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> Hello,
>
> I was just building version 3.1.0 and ran into some problems in DOScreen.cpp. Basically the conversions from
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Thu Jun 2 21:01:29 2011, Stefan Ritt, Removing spikes
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Martin Petriska wrote:
I have DSR4 eval board. Found that there are spikes in channels. Procedure Osc::RemoveSpikes to remove |
Tue Jul 5 10:09:43 2011, Stefan Ritt, Fixed Patter Timing Jitter
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Jinhong Wang wrote:
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Wed Jul 13 04:26:52 2011, Stefan Ritt, Fixed Patter Timing Jitter
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Jinhong Wang wrote:
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Wed Sep 7 16:56:43 2011, Stefan Ritt, DRS4 and AD9222
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Guillaume Blanchard wrote:
Normal
0
21
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Fri Sep 9 09:31:33 2011, Stefan Ritt, DRS4 and AD9222
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Guillaume Blanchard wrote:
Thank you for your answers, |
Mon Sep 19 08:53:22 2011, Stefan Ritt, compilation error for version 4.0.0 on linux
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Andriy Zatserklyaniy wrote:
To fix it I added TriggerDialog.o into CPP_OBJ line of the Makefile: |
Sat Oct 22 00:40:02 2011, Stefan Ritt, DRS4 eval board: readout rate
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Aurelien Bouvier wrote:
Hi, |
Mon Oct 24 10:30:15 2011, Stefan Ritt, Phase Shift for ADC Readout
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Hao Huan wrote:
Dear Dr. Ritt, |
Tue Nov 1 11:07:02 2011, Stefan Ritt, How to link PMT
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Zhongwei Du wrote:
I want to measure the signal from PMT . But it is a current signal, should i just put a series resistance, |
Mon Dec 12 16:43:04 2011, Stefan Ritt, DC coupled DRS4 input stage
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In the attachement you will find a working DC-coupled input stage to the DRS4 chip. The bandwidth of this design is about 700 MHz, the gain is 1.
The upper version does not have an additional input buffer. This is not a very "clean" design, since the differential driver has an input
impedance of 150 Ohm, which together with the 75 Ohm termination resistor gives about 50 Ohm termination. |
Wed Dec 14 08:55:29 2011, Stefan Ritt, Synchronization Delay in the Firmware for 8051 Controller
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Hao Huan wrote:
Hi Stefan, |
Fri Jan 20 08:09:38 2012, Stefan Ritt, drs_exam.cpp for evaluation board version 4
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Heejong Kim wrote:
Hello, |
Thu Jan 26 09:15:42 2012, Stefan Ritt, DRS4 Rev2.0 for analog pulse counting
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Ravindra Raghunath Shinde wrote:
Hello, |
Thu Jan 26 09:49:38 2012, Stefan Ritt, DRS4 Rev2.0 for analog pulse counting
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Ravindra Raghunath Shinde wrote:
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Tue Jan 31 08:10:37 2012, Stefan Ritt, IEEE Real Time 2012 Call for Abstracts
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Hello,
I'm co-organizing the upcoming Real Time Conference, which covers also fields of waveform processing and sampling, so it might be interesting for
people working with the DRS4 chip. If you have recent results, you could also consider to send an abstract to this conference. It will be nicely |
Mon Feb 6 08:15:38 2012, Stefan Ritt, what sort of detectors for physical experiment the DRS4 used?
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Zhongwei Du wrote:
Hello. |
Fri Feb 24 15:52:43 2012, Stefan Ritt, DRS4- analog pulse counting
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sonal wrote:
Hello Sir, |
Thu Mar 1 19:22:26 2012, Stefan Ritt, DRS4- analog pulse counting
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Sonal wrote:
The DRS4 Rev.2.0 with one Multiplexer and a Comparator I think may be is ok for me. Since I wanted to implement counter in FPGA, I have gone |
Tue Mar 20 16:33:50 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Martin Petriska wrote:
I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger |
Wed Mar 21 09:39:33 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Martin Petriska wrote:
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Wed Apr 25 13:42:37 2012, Stefan Ritt, DRS4 Initialization
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Guillaume Blanchard wrote:
Hello, |
Wed Jun 20 12:45:05 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Ivan Petrov wrote:
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Wed Jun 20 14:44:38 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Ivan Petrov wrote:
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Mon Jun 25 14:21:13 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Andrey Kuznetsov wrote:
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Tue Jul 10 13:15:00 2012, Stefan Ritt, Problem compiling drs_exam.cpp on windows
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Ivan Petrov wrote:
Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to |
Mon Aug 6 02:44:00 2012, Stefan Ritt, Calculation of loop filter parameters (R,C1and C1) for 1 GHz
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Mayank S. Rajguru wrote:
Hi, |
Wed Aug 29 10:52:44 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp
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Zach Miller wrote:
Hi, |
Wed Aug 29 16:45:36 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp
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Zach Miller wrote:
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Thu Oct 4 20:59:18 2012, Stefan Ritt, DRS5
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Zach Miller wrote:
Hi, |
Fri Oct 12 14:09:37 2012, Stefan Ritt, DRS abbreviation
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Moritz von Witzleben wrote:
Hello, |
Thu Nov 1 20:17:42 2012, Stefan Ritt, DRS4 firmware
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hongwei yang wrote:
Hi, |
Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware
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hongwei yang wrote:
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Tue Nov 13 11:26:32 2012, Stefan Ritt, GetWave
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Martin Petriska wrote:
I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) |
Wed Nov 21 08:38:26 2012, Stefan Ritt, Question for using Multi board
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Gyuhee Kim wrote:
Hi. |
Wed Nov 28 16:54:46 2012, Stefan Ritt, DRS Oscilloscope for Raspberry Pi and Mac OSX 10.8
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I made a pre-compiled package for Mac OSX 10.8 (Mountain Lion), so one should be able to install the DRS Oscilloscope software with one mouse click on
a recent Mac.
The Makefile in the tar ball now also supports OSX 10.8, so one could even compile it from the sources on a Mac, after libusb-1.0 and wxWidgets |
Mon Dec 3 09:18:09 2012, Stefan Ritt, Another question about using multi boards.
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Gyuhee Kim wrote:
Hi. |
Tue Dec 4 09:39:44 2012, Stefan Ritt, Question of drs4 using
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Zhongwei Du wrote:
When Denable and Dwrite is high , the voltage of PLLOUT is 0 V. And the Dtap is turn high |
Tue Dec 4 09:55:43 2012, Stefan Ritt, Question of drs4 using
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Zhongwei Du wrote:
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Thu Dec 13 12:14:35 2012, Stefan Ritt, DRS-4 trigger
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Evgeni wrote:
How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed |
Fri Dec 14 08:42:53 2012, Stefan Ritt, DRS-4 trigger
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Evgeni wrote:
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Fri Dec 14 21:49:29 2012, Stefan Ritt, EVM rev4 board trigger change and drs_example
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Martin Petriska wrote:
I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting |
Thu Dec 27 09:49:17 2012, Stefan Ritt, variation of sampling capacitors
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Jinhong Wang wrote:
Hi Stefan, |
Tue Feb 5 14:38:35 2013, Stefan Ritt, variation of sampling capacitors
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Jinhong Wang wrote:
Hi Dr. Stefan, |
Wed Feb 13 17:03:53 2013, Stefan Ritt, Nonuniform sampling
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Martin Petriska wrote:
Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly |
Fri Feb 22 11:56:57 2013, Stefan Ritt, DRS4 trigger, different polarity
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Yury Golod wrote:
Normal
0
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Thu Feb 28 12:58:44 2013, Stefan Ritt, clock and trigger outs
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> Hi,
> I am considering using the DRS4 evaluation board as an ADC card for the wire chamber in the physics lab (VP) experiment at ETH. However, the wire
> chamber has 8 outputs, so I would need to have two of such boards. Is it possible to synchronise them, online or offline? From the website, it looks |
Wed Mar 6 12:37:14 2013, Stefan Ritt, DRS4- analog pulse counting
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Osip Lishilin wrote:
Hello, Stefan. Have you implemented pulse counting yet? |
Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error
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Georg Winner wrote:
When starting Chip Test in DRS Command Line Interface, I receive the following message: |
Thu Apr 4 11:21:04 2013, Stefan Ritt, Differences in Source Code
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Georg Winner wrote:
I have noticed some differences in the source code between Windows (4.0.0) and Linux (4.0.1) Version. |
Thu Apr 4 11:32:21 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp
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Jill Russek wrote:
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Fri Apr 5 08:54:37 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp
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Jill Russek wrote:
Would it be possible to just hardcode a few lines in the SetChannelConfig in DRS.cpp method as such: |
Thu Apr 11 08:39:12 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp
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Jill Russek wrote:
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Fri Apr 12 08:25:05 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp
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Jill Russek wrote:
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Fri Apr 12 08:38:17 2013, Stefan Ritt, code/details for optimal DRS4 timing calibration?
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Bill Ashmanskas wrote:
Hi Stefan, |
Mon Apr 22 15:52:53 2013, Stefan Ritt, effect of jitter/alignment between SRCLK and ADC clock
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Benjamin LeGeyt wrote:
Hello! |
Tue May 21 13:25:41 2013, Stefan Ritt, mac osx 10.6
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> Hi,
>
> I would like to use the DRS4 with my macbook pro running osx 10.6.8.
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Tue May 21 17:51:09 2013, Stefan Ritt, mac osx 10.6
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> >
> > it looks like 64bit vs 32bit problem, you have to compile all libraries for the same architecture. Maybe, make clean to
> > remove all precompiled object files .o and recompile it again. Try to compile first that simple example without wxWidgets.
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Fri May 24 18:20:14 2013, Stefan Ritt, mac osx 10.6
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> I made some progress. Understood what was wrong in the make phase. You have only to add the option -arch i386 in the CFLAGS line of the makefile.
> Then the make is ok, it produces the 3 executables. drs_exam and drscl seem to work correctly.
> DRSOsc.app does not work as app, in the sense that if you click it, an error message comes saying "You can't use this version of the application DRSOsc.app |
Sat May 25 21:03:22 2013, Stefan Ritt, DRS4- analog pulse counting
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Osip Lishilin wrote:
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Fri Jun 7 10:22:48 2013, Stefan Ritt,
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tmiron alon wrote:
Hallo, |
Mon Jun 10 16:24:21 2013, Stefan Ritt, add an average ability to the Scope
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tmiron alon wrote:
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Tue Jun 18 14:19:39 2013, Stefan Ritt, ROOT program to decode binary data from DRSOsc
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Please find attached a simple ROOT based program (http://root.cern.ch) to decode binary data from the DRSOsc program. It assumes that all four channels
were recorded. If this is not the case, the program can be adjusted accordingly.
To use it, simply type (assuming that you have written a data file "test.dat" with DRSOsc): |
Thu Jul 4 08:54:25 2013, Stefan Ritt, add an average ability to the Scope
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tmiron alon wrote:
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Thu Jul 4 09:17:31 2013, Stefan Ritt, add an average ability to the Scope
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tmiron alon wrote:
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Thu Jul 4 10:14:32 2013, Stefan Ritt, add an average ability to the Scope
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tmiron alon wrote:
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Sat Jul 6 06:10:38 2013, Stefan Ritt, Missing methods in drs-4.0.1.tar.gz
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Hermann-Josef Mathes wrote:
Hi, |
Tue Jul 9 12:23:06 2013, Stefan Ritt, cannot save in binary format
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Dmitry Hits wrote:
Hi, |
Tue Jul 16 16:25:43 2013, Stefan Ritt, add an average ability to the Scope
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tmiron alon wrote:
Hi Stefan. |
Tue Jul 23 22:35:08 2013, Stefan Ritt, Evaluation Board Behavior
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alonzi wrote:
Working with the DRS evaluation board we noticed some funny behavior: See attatchment 1. In about 1% of scope traces we see the first and |
Mon Jul 29 06:04:45 2013, Stefan Ritt, add an average ability to the Scope
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Hi satefan,
I did some debug on the DRSOsc program and saw that everywhere you used the function "IsBusy()", you used it with "SoftTrigger()", |
Wed Aug 7 15:10:57 2013, Stefan Ritt, Repeated time calibration
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Hermann-Josef Mathes wrote:
Hi, |
Mon Aug 12 22:18:39 2013, Stefan Ritt, add an average ability to the Scope
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tmiron alon wrote:
Right now I'm trying to speed up the number of wavefrom per second. I'm using your drs_exam.cpp |
Mon Sep 23 09:26:56 2013, Stefan Ritt, Sampling Frequency: DRS4 eval board
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Andrzej Rychter wrote:
Is it possible to set sampling frequency at 100 MHz in DRS4 eval board? Trying to set 0.1GHz in Osci |
Wed Nov 6 12:25:31 2013, Stefan Ritt, flickering screen for drsosc
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Dmitry Hits wrote:
Hi, |
Wed Nov 6 16:35:42 2013, Stefan Ritt,
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lengchongyang wrote:
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Thu Nov 14 12:51:56 2013, Stefan Ritt, Cascading of channels
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Schablo wrote:
Hello, I want use cascading of channels for 2048 cell - SetChannelConfig(0,8,4), but i can't understand how . Please, help me. |
Mon Nov 18 16:00:26 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis
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Dmitry Hits wrote:
Dear Stefan, |
Tue Nov 19 09:09:01 2013, Stefan Ritt, DRSOsc at Mac OS X Mavericks
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Andriy Zatserklyaniy wrote:
I installed Mac OS package on macbook (late 2013). DRSOsc starts to write file but freezes; need to |
Wed Nov 20 08:16:10 2013, Stefan Ritt, DRSOsc at Mac OS X Mavericks
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Andriy Zatserklyaniy wrote:
When I launch DRSOsc.app/Contents/MacOS/DRSOsc from terminal, I see constantly pouring messages |
Thu Nov 21 14:45:56 2013, Stefan Ritt, Cascading of channels
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Schablo wrote:
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Tue Nov 26 15:38:13 2013, Stefan Ritt, reducing sampling speed
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Dmitry Hits wrote:
Dear Stefan |
Tue Dec 10 14:54:46 2013, Stefan Ritt, measurement range
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ismail okan atakisi wrote:
I m trying to measure lifetime in our lab and I intend to take |
Fri Dec 13 11:37:58 2013, Stefan Ritt, input protection in DRS4 evaluation board
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Dmitry Hits wrote:
Last month I was using a DRS4 evaluation board to digitise the signal from the charged particles in |
Tue Dec 17 08:45:32 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis
|
Dmitry Hits wrote:
|
Thu Jan 9 11:02:46 2014, Stefan Ritt, v5 software with v4 board calibration
|
Martin Petriska wrote:
Hi |
Wed Jan 15 14:20:51 2014, Stefan Ritt, Announcement of new Evaluation Board V5
|
Dear DRS community,
starting from this year, we ship the new evaluation board V5. This board has an improved internal timing calibration, with which one can measure
the time with a precision down to a few ps. Following picture shows the time between two pulses, obtained with a function generator, a passive split and |
Wed Jan 15 15:48:55 2014, Stefan Ritt, USB connection stops
|
Hi,
finally I found some time to look into this problem, sorry for the late delay.
|
Wed Jan 15 16:15:00 2014, Stefan Ritt, Some bug fixes and questions
|
Andrey Kuznetsov wrote:
For http://www.psi.ch/drs/DocumentationEN/manual_rev20.pdf: |
Wed Jan 15 17:02:58 2014, Stefan Ritt, Some bug fixes and questions
|
Andrey Kuznetsov wrote:
So although it doesn't affect data retrieval, it's just dumb luck the function ends up being called |
Wed Jan 15 17:11:14 2014, Stefan Ritt, Some bug fixes and questions
|
Andrey Kuznetsov wrote:
The DRSCallback *pcb is missing an if statement in the code when DRS Oscilloscope software |
Wed Jan 15 17:34:55 2014, Stefan Ritt, DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program
|
Andrey Kuznetsov wrote:
Hi, |
Wed Jan 15 17:37:21 2014, Stefan Ritt, DRS4 installation on Windows 8 issues
|
Andrey Kuznetsov wrote:
I'm also having trouble installing drivers and running DRSOsc program |
Wed Feb 5 13:41:42 2014, Stefan Ritt, Repeated time calibration
|
Hermann-Josef Mathes wrote:
Hi Stefan, |
Tue Feb 18 14:12:37 2014, Stefan Ritt, Announcement of new Evaluation Board V5
|
Stefan Ritt wrote:
Dear DRS community, |
Thu Mar 6 11:12:44 2014, Stefan Ritt, Software drs-5.0.0 fails to compile (drsosc)
|
Hermann-Josef Mathes wrote:
Hi, |
Wed Apr 16 08:20:36 2014, Stefan Ritt, drs_exam project fail to compile
|
Carlo Stella wrote:
Hi, |
Wed Apr 16 08:30:32 2014, Stefan Ritt, why is the first channel output error?
|
Wang wrote:
Hi, |
Wed Apr 16 10:24:55 2014, Stefan Ritt, DRS4 Evalboard V5 with Windows7Pro64bit
|
>
> Dear Stefan
>
|
Tue May 13 19:39:36 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion
|
Luka Pavelic wrote:
Hi, |
Tue May 13 23:08:50 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion
|
Luka Pavelic wrote:
Thank you for your fast and very helpful replay. |
Mon May 19 08:04:57 2014, Stefan Ritt, simultaneous writing and reading with region of interest mode?
|
Benjamin LeGeyt wrote:
Hello! |
Tue May 27 16:07:17 2014, Stefan Ritt, Spikes in DRS4 data on custom baord.
|
Dominik Neise wrote:
We see quite some spikes in our DRS4 sampled data in FACT. We see different types of spikes: |
Wed Jun 11 11:13:50 2014, Stefan Ritt, Announcement of new Evaluation Board V5
|
Osip Lishilin wrote:
|
Thu Jun 12 12:46:00 2014, Stefan Ritt, DRS eval bord v5 Timing
|
> a) Calibration:
> I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For
all
|
Thu Jun 12 17:16:13 2014, Stefan Ritt, CalibrationWaveform
|
Toshihiro Nonaka wrote:
I'm writing the drs_exam.cpp to use multi-boards(v3, firmware:4.0.0), and taking data succeeded. But |
Wed Jul 16 12:10:19 2014, Stefan Ritt, change cascading from 1024 to 2048 bins for each input channel
|
Yves Bianga wrote:
Hello, |
Wed Jul 30 17:05:06 2014, Stefan Ritt, ROOT program to decode binary data from DRSOsc
|
Stefan Ritt wrote:
Please find attached a simple ROOT based program (http://root.cern.ch) to decode binary data from the |
Wed Jul 30 17:05:38 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion
|
ChengMing Du wrote:
|
Tue Aug 26 12:32:21 2014, Stefan Ritt, 10GSps on DRS4 Evm with delay cables
|
Martin Petriska wrote:
Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048). |
Fri Sep 12 13:00:04 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer
|
Dmitry Hits wrote:
Hi everyone, |
Fri Sep 12 13:41:43 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer
|
Dmitry Hits wrote:
|
Fri Sep 12 16:08:49 2014, Stefan Ritt, compilation error for v5.0.2
|
Dmitry Hits wrote:
Hi, |
Mon Sep 22 14:52:21 2014, Stefan Ritt, compilation error for v5.0.2
|
Dmitry Hits wrote:
|
Mon Sep 22 15:04:37 2014, Stefan Ritt, Timing Calibration Fail
|
Hannes Wachter wrote:
Hi, |
Mon Oct 13 16:46:56 2014, Stefan Ritt, USB Microcontroller firmware
|
Stephane Debieux wrote:
Hi, |
Mon Oct 13 17:14:58 2014, Stefan Ritt, USB Microcontroller firmware
|
Stephane Debieux wrote:
|
Tue Oct 14 16:29:12 2014, Stefan Ritt, USB Microcontroller firmware
|
Stephane Debieux wrote:
|
Tue Oct 14 16:38:14 2014, Stefan Ritt, USB Microcontroller firmware
|
Stephane Debieux wrote:
|
Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ
|
Simon Weingarten wrote:
Hi, |
Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ
|
Here is the full version of the program with clock daisy-chaining. Before switching to the external clock, it checks if the clock really
is there (by reading an internal scaler), and only then enables it. Note that the code also works without clock daisy-chaining. But without clock daisy-chaining
your have some 400 ps time resolution between boards, and with clock daisy-chaining you get some 60 ps. |
Thu Oct 16 16:15:16 2014, Stefan Ritt, binary files with more than 4 drs board ver. 5.0.2
|
> Dear Stefan
>
> after having some problems with writing binary files with more than 4 drs boards (in multiboard-mode) I might
|
Thu Oct 16 16:16:12 2014, Stefan Ritt, binary files time calibration header in drs-5.0.2
|
> Dear Stefan
>
> I have a problem considering binary data files.
|
Tue Nov 25 14:06:34 2014, Stefan Ritt, Raspberry Pi drsosc does not exit properly
|
Mickey Chiu wrote:
When running drsosc on a raspberry pi, it seems the exit doesn't seem to work at all. This is |
Fri Jan 16 14:12:19 2015, Stefan Ritt, Mac OSX Yosemite 10.10
|
> Hello,
>
> I can compile version 5.0.3 of DRS4sc on Mac OSX 10.0 without errors but when I want to execute the program I get the following error:
|
Tue Mar 17 02:53:26 2015, Stefan Ritt, Running 2 instances of a DRS DAQ program
|
I never had in mind running two systems in parallel, that's why the code claims all interfaces when started. You have to dig into the usb code which
is located in musbstd.c at function musb_open(). There you will find a line libusb_claim_interface() which requests exclusive access to the usb subsystem.
The code is there because I copied it from some standard example for the libusb library. You have to read the documentation for libusb (http://libusb.sourceforge.net/api-1.0/) and |
Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ
|
The resolution coming from the sampling rate goes into these numbers, but just marginally. At 5 GSPS, you get a few ps reolution, while at 1 GSPS, you
get like 15 ps. If you convolve 15 ps with 400 ps, you get 400.3 ps, which is not significantly worse than 400 ps.
Simon |
Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource
|
Your first assumption is correct, e.g.
source = 00000000'00000001 = 0x0001 ==> CH1
source = 00010001'00000000 = 0x1100 ==> CH1 and EXT |
Tue Apr 21 12:52:18 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration
|
1) I tried to cablirate a V5 board with drsosc 5.0.3 and it just worked fine for me. No idea what went wrong in your case.
2) The "found 4096 stuck pixels on this board" can be safely ignored. It comes from the fact that the standard evaluation board has
four cannels unconnected (the DRS4 chip has 8 channels, four are connected to in the evaluation board and four are unconnected). So the software sees |
Tue Apr 21 13:06:39 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration
|
Sure, for a V3 board you need a pre-V5 software, but I assumed Julien had a V5 board.
Daniel
Stricker-Shaver wrote:
I also use Ubuntu 14.04 LTS and for my V3 borad I have to |
Wed May 13 08:19:53 2015, Stefan Ritt, Getting Trigger Source
|
DRSBoard::GetTriggerSource() simply returns what has been enabled via DRSBoard::SetTriggerSource(). The actual source which causes the trigger is not
stored in the hardware of the board, because I can be reconstructed easily from the waveforms. So just look which of the channels is above your trigger
threshold. If none of the channels has a waveform obove the threshold, then the trigger must have been come from the external trigger. |
Wed May 13 09:45:51 2015, Stefan Ritt, transparent-mode voltage
|
The ROFS signal has no effect in the transparent mode, so you have to adjust O_OFS between sampling and transparent mode accordingly. Either use a DAC
or two voltages with an analog switch.
Chenfei |
Wed May 13 10:16:40 2015, Stefan Ritt, transparent-mode voltage
|
I see your point. Actually I will soon have the same issue since we design right now a board with an AD9637 using the transparent mode. Which one are
you using? The common mode range given in the datasheet is limited to guarantee optimal performance. But some ADCs allow a slightly bigger common mode
range with reduced performance, but which might still be ok for some application. A "real" solution would be to put switchable level shifters |
Wed May 13 12:34:49 2015, Stefan Ritt, transparent-mode voltage
|
There might be a solution. How do you bias th input of the DRS4 chip? If you use a scheme as described in elog:84,
you can bias DRS_IN+ and DRS_IN- as desired. Take for example a board input range of 0-1V. For a 0V input, you bias DRS_IN+ and DRS_IN- both
with 0.9V. A 1V input signal then puts DRS_IN+ to 1.4V and DRS_IN-to 0.4 V. In the transparent mode, DRS_OUT+ = DRS_IN+ and DRS_OUT- = O-OFS |
Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage
|
To get the good linearity, you need indeed ROFS = 1.05V. With a O-OFS of 0.9V, a zero input signal would give you DRS_OUT+=1.05V and DRS_OUT-=0.75V.
I think this is till in the range of your ADC, right? So it's a tradeoff between linearity and available range. I do not know how nonlinear the DRS4
will be for ROFS < 1.05V, you have to try. If it's getting too bad, you still can correct for this off-line. |
Fri May 22 14:25:45 2015, Stefan Ritt, DRS4 firmware UCF constraints
|
> Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
>
> I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
|
Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB
|
First of all, you should not use new boards with old software. I try to keep the current software compatible with old boards, but not vice versa. Please
use the DRS.cpp library from the current V5 software, otherwise your time calibration will not work.
If you then do the calibration with the V5 software and the V5 board, you will see that the bin widhts of the DRS chips are not the same. Actually |
Fri Jun 5 12:07:38 2015, Stefan Ritt, DRS4 firmware UCF constraints
|
I presume you have several evaluation boards and want to run them in sync, right?
This can be either made in daisy-chain mode (see manual page 25). In this case only the master board can trigger the slave boards. If you need to trigger |
Fri Jun 5 13:29:55 2015, Stefan Ritt, DRS4 firmware UCF constraints
|
Do the following:
Use the TRG OUT of the evaluation board as a "busy". Only if this signal goes low (meaning that the readout of the board is complete and the board has |
Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints
|
Actually we should take this offline not to pester other DRS users which are not interested in this topic. Please call me directly (3728) at PSI.
/Stefan |
Tue Jun 16 22:26:41 2015, Stefan Ritt, DRS4 Evaluation Board Osc Application
|
There is a horizontal position slider in the "Horizontal" box on the right side below the trigger delay. Use it.
Michael
Buadelk wrote:
Hi, I have a DRS4 v5 evaluation board and I have a novice question |
Fri Jul 3 17:13:27 2015, Stefan Ritt, Creation of Object files
|
Hi Felix,
the distribution does not contain any binaries, since there are too many Linux distributions around, so everybody compiles from the sources under
Linux. Do you want me to just add libDRS.so to the official Makefile? Actually you are the first one asking for this. Would it be beneficial to have this |
Mon Jul 6 19:25:27 2015, Stefan Ritt, Creation of Object files
|
Anyhow it would be nice if you just post your Makefile here, which runs with the standard distribution, so people can use it if needed.
Stefan
Felix |
Thu Jul 23 13:46:12 2015, Stefan Ritt, Measure the time between different samples
|
> Hi,
> I have a question using a data acquisition card base on DRS4 chip. How can I measure the time between several samples of one channel,with the
accuracy of like nanoseconds , for I am using the internal trigger. Is there any complete work about this problem?
|
Wed Nov 4 15:40:10 2015, Stefan Ritt, Latest macro for DRS4 V5
|
Have a look here: elog:361
Will |
Wed Nov 25 08:20:47 2015, Stefan Ritt, PC software beyond Windows 7
|
Have a look here elog:434
Chris
Thompson wrote:
I am new to this forum. I have ordered a DRS4 evaluation board for |
Wed Dec 23 15:48:42 2015, Stefan Ritt, Dtap stops toggling after 40msec
|
No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?
mony
orbach wrote:
Hi |
Thu Dec 24 12:45:41 2015, Stefan Ritt, Dtap stops toggling after 40msec
|
I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.
Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong
capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem |
Mon Dec 28 11:05:15 2015, Stefan Ritt, Dtap stops toggling after 40msec
|
Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register
is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins.
So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually |
Wed Dec 30 17:00:00 2015, Stefan Ritt, Dtap stops toggling after 40msec
|
While I can understand 1., I'm puzzeled by 2.
If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This
is clearly stated in the data sheet. |
Tue Jan 12 12:57:46 2016, Stefan Ritt, PC software beyond Windows 7
|
The 5.0.4 version was corrupt on our server. I fixed it, so now it shoudl also work fine (although there are only very minor changes between 5.0.3 and
5.0.4).
/Stefan |
Tue Jan 12 16:06:07 2016, Stefan Ritt, Use of Channel Cascading in drs_exam.cpp
|
Hi Larry,
sorry my late reply, swamped with work here. You were right in the modifictions you did, congrats. The speed limitation of 500 events come from
USB2, which simply is not fast enough. The 500 Hz are mentioned on the evaluation board web site, so you should have seen that before ordering. Some people |
Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam
|
I guess you are compiling under MS Windows ??? You probably don't link correctly to the USB lib. Try to compile the examples coming with libusb-1.0
to make you everything is right there.
Jack |
Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec
|
Thanks for the update, I will add a note into the data sheet.
mony
orbach wrote:
surrey i forgot to update.. |
Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode
|
Hi Chris,
if you ever used an oscilloscope, you might be familar with the button controlling the riger in respect to "risign edge" vs. "falling
edge". I copied the same for the DRS software. So just click on that button: |
Tue Feb 16 11:21:43 2016, Stefan Ritt, Saving histogram data
|
There is no histogram save functoinality in ther DRSOscilloscope program - on purpose. The board and the software are meant to evaluate the board, not
to replace a full DAQ system. If we want to save histograms, you maybe also want to set the range, make cuts, do fits etc. So it would take lots of resources
to add all that. Therefore we recommend to use the stand-alone C program drs_exam.cpp to read the board, the you can either do whatever you want in the |
Mon Feb 29 13:09:29 2016, Stefan Ritt, baseline shift
|
The baseline shift comes from some instable power supply inside the evaluation board which cannot be controlled to the mV level. In a real measurement,
you usually get an additional baseline shift due to some environmental electromagnetic interferences, such as a 50 Hz signal. People fix this shifting
baseline by always aquiring a small portion (10-20 samples) of the baseline before any signal from a particle detector. The signal is then corrected event-by-event |
Mon Feb 29 14:09:21 2016, Stefan Ritt, two DRS4 boards configuration with 2048 samples each
|
The multi-board mode has never been tested with 2048 samples, so is very likely not to work. I don't know yet how much work this will be to
fix, but I'm on a business trip the next three weeks and probably will only have time to look at it when I return.
Stefan |
Tue Mar 22 12:54:41 2016, Stefan Ritt,
|
Yes this is correct. But it is a sample-and-hold circuit. So the sampling cell follows the input for 3.2 ns, then samples and holds the current value
at the end of the period.
Dominik |
Thu Mar 31 19:35:06 2016, Stefan Ritt, Trigger on the And of a positive and negative signal
|
No. You have to use an inverter for one of your signals.
Stefan
Abaz |
Thu Mar 31 20:34:25 2016, Stefan Ritt, Trigger on the And of a positive and negative signal
|
Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups
Abaz
Kryemadhi wrote:
Ok, thanks! do you know an easy in-line inverter like mini-circuit |
Sat Apr 2 11:41:07 2016, Stefan Ritt, Question about timimng calibration
|
The evaluation board normally has 1024 bins per channel. We offer an option with 2048 bins using channel cascading, to capture longer waveform windows.
The binary data format is however defined as having 1024 bins. Therefore, for the 2048 bin boards, the software averages over two adjacent cells and saves
effectively 1024 bins. The noise of each bin improves this way by sqrt(2). The time however is not very well defined, since you average the voltage of |
Mon Apr 4 11:31:34 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run
|
Dear Daniel,
sorry my late reply, I'm pretty busy these days. The behavior you report has not been seen before, but I guess no one tried to take such
long runs of data yet. Can you confirm that the problem also occurs without writing data to disk, or is it disk-related? I guess you use it under Windows |
Mon Apr 4 12:08:15 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run
|
Then it seems that there is some USB communication problem. I heard this also from other people, that the USB data transfer under Windows has sometimes
problems. I develop and run the board under Mac OSX, and there the same software runs for days without problem. So I guess it's related to the underlying
libusb lib which is used by the DRS oscilloscope, on which I have no influence. So the only advice I can give is to take shorter series of data. Anyhow |
Tue Apr 5 16:08:59 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run
|
I tried this night to run the board at a 10 Hz rate with an external pulser, without writing, and it did not freeze after ~14 hours of running on Mac
OSX. This night I will try again with writing.
Stefan |
Wed Apr 6 08:41:08 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run
|
Even with writing for one night no problem (see below). Have you checked how big your data file is? I guess there is a limit under Windows of 2 GB. If
that's the case, you have to write shorter files.
|
Tue Apr 26 09:54:16 2016, Stefan Ritt, Negative fCellDT values from GetTimeCalibration()
|
I just realized that the negative bin widht is not explicitly mentioned in the quoted paper. So let me explain it here:
The negative value of cell 498 is correct and "real" in the sense that the signal is first captured in cell 498 and later
in cell 497. This is due to the exact layout of the cells on the chip and the input signal. Cell 498 is simply much closer to the input, so sees the |
Tue Apr 26 13:42:42 2016, Stefan Ritt, DRS4 purchase information
|
Just be patient. Anita is not at work this week.
Konstantin
Gusev wrote:
Hi, |
Wed Apr 27 09:04:01 2016, Stefan Ritt, serial number problem
|
If dis- and reconnecting the board does not help, there is the (small) chance that the serial number got erased in the board. You can re-set it with
the "drscl" command line tool:
$ drscl |
Thu Apr 28 15:46:34 2016, Stefan Ritt, Best settings for time measurements
|
The DRS4 chip has been designed to work best at high sampling speeds. At 700 MSPS, the chip is at it's limit and timing is very poorr (ns?). In order
to get good timing, run it at least at 2 GSPS.
Stefan |
Thu Apr 28 15:47:53 2016, Stefan Ritt, New software version and binary format
|
A new software version 5.0.5 has been released today. This fixes a few bugs in multi-board configurations, and adds saving of the scaler values into
XML and binary files. Please note that the binary file format has been changed for that. The new format is described in an updated manual (page
25), and reflected in a new read_binary.cpp program contained in the distribution. |
Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download
|
Can you tell me (screendump) what is the problem on the web site https://www.psi.ch/drs/software-download ?
It should redirect you to
https://www.dropbox.com/sh/qul1cgtm4x7zx13/AADKQ-qGQGdAHPu6OR3vTNY0a?dl=0 |
Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events
|
Dear Maksat,
If your car does not run, and you call the car dealer and tell him "my car does not run", what will the car dealer ask you? Eh... ?
Right ! He will ask "what are the symptoms, what did you try, what did and what did not work". Here it's the same. "was not able to |
Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??
|
I cannot confirm the story with the "stop capacitor > 767". It can be seen from your plots that the distribution of stop cells are even,
no holes or bins with double height.
There is an issue with cell 767, but this is when one tries to do simultaneous reading/writing to the chip. This does not really work as writen |
Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4
|
1. Simultaneous writing and reading is not possible with the DRS4 chip. The manual says differently on p. 14, but due to a bug in the chip waveforms
get clipped at the end if one does that. We hopt to fix this problem in a future version of the chip.
2. You can cascade 2,4 or 8 channels. If you cascade 8 channels and run at 1 GSPS, you digitize a window of 8 us. If you have 16 signals, you |
Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals
|
Hello everybody,
I get often asked if the DRS4 evaluation board can accomodate negative input pulses going to -1V. This is unfortunately not possible, since the
board is mainly for evaluation of the DRS4 chip and should not be seen as a complete oscilloscope with flexible input stage. So the maximum it can do is |
Mon Aug 29 10:57:33 2016, Stefan Ritt, increment write config register on the fly?
|
The issue with "stopping at cell 767" would also affect this mode of operation. Furthermore, the DRS4 chip has only 10 bit register which
records in which cell the event has occured, and where the readout must be started. If you record 8 separate events, you don't know where to start
the readout. |
Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly?
|
The problem is when you change the write config register from 11111111 to 01111111, or from 00001111 to 00000111, then the last 256 sampels of the previous
channel (in the first case #0, in the scond #4) would be overwritten as soon as dwrite =1 again. So you loose 1/4 ef each channel.
Concerning the readout, indeed you can keep track in the FPGA, but only with a certainty of a few cells. This gives some timing inacccuracy of |
Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting
|
Hi Jacob,
you are missing the timing calibration. Each sampling cell has not the same width. Running at 5 GSPS, cell widths scatter from 150 ps to 250
ps. If you integrate these widhts, you get a time scale which can be off by a few ns between chips, something you see in your plot. Here is a paper which |
Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform
|
In the mentioned read_binary.cpp file you have the line where you read the event header
i = fread(&eh, sizeof(eh), 1, f);
The C structure eh now contains the full timestamp, and you can access it with |
Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Can you post a screenshot of your measurement?
Stefan
Danny |
Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Ok, I got it. The timing resolution is affected by the signal-to-noise ratio over the rise-time of your signal. You find the full formula herer:
https://arxiv.org/abs/1405.4975
Your sine wave input signal has a slow rise time, and therefore limits the time resolution. I reproduced your measurement with a 20 MHz sine |
Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker at the
very left side of the screen, where the yellow marker is at a different position as the others. Hint: a right-click on that slider sets it to zero. The
little streak could be some kind of external noise. |
Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker |
Thu Oct 27 08:29:26 2016, Stefan Ritt, Problems with DRS command line
|
[quote="Alexey Lubinets"]Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
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Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line
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No, I absolutely have no idea. Both DRSOsc and drscl use exaclty the same code to access USB.
Stefan
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Tue Nov 8 10:20:52 2016, Stefan Ritt, Missing Header
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The web page from where you downloaded the software contains a sentence "requires libusb-1.0 package". Please install it. This package brings
the "usb.h" header file.
Stefan |
Wed Nov 9 19:49:07 2016, Stefan Ritt, Missing Header
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Best is to read this paper: https://arxiv.org/abs/1405.4975
The source code for that is in DRS.cpp in the DRS software distribution in the function DRSBoard::CalibrateTiming()
Stefan |
Thu Nov 10 09:56:04 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro
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Hi,
fread() returns the number of bytes read and zero (I believe) if there is an end of file. So this break statement is a simple end-of-file test.
There might be other erros such as hard disk failures, but these are extremely rare. |
Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro
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You're right, fread() return the number of objects read, so indeed it should be one if successful.
Abhishek
Rajput wrote:
Hello, |
Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()
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Cell 700 is arbitrary. You can choose any cell to align the channels to each other. The only requirement is that it's always the same cell for each
event. Historically, Daniel chose cell #700 more or less arbitrary, but later we found out that this works with any cell. So for the publication we went
with cell #0 (and that's why we have t_ch,0 in the paper), but cell #700 was left in the code because of lazyness. Feel free to replace 700 with any |
Thu Nov 24 08:13:23 2016, Stefan Ritt, PLL did not lock
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Which serial number has the board? Has it been in use before or is it a new board?
Stefan
Alexey |
Thu Nov 24 13:24:26 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data
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The code in the macro is correct. The misconception lies in the definition what "sample 0" means. Please view the attached picture. This is
simplified case with a DRS chip with only 8 cells (instead of 1024). There are two events (blue and red). In the first event, the chip is stopped at trigger
cell (tc) 2, in the second case at 5. Since the readout starts with the trigger cell, the first readout sample in the first event belongs to cell #2, the |
Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock
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Have you tried to unplug and re-plug the board a few times? According to our database, you should have three boards. Do all three show the same behavior
or only this board? In case all three show this, it could be a hint of a software problem. If two boards are good and one is bad, this would be a hint
of a hardware problem (broken board). |
Wed Nov 30 08:53:58 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data
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The inverter chain in the DRS4 is continously running in a ring. Once you get a trigger, it is stopped. This happens in any of the 1024 cells. The last
cell which sampled a signal plus ne is called "trigger cell". In the previous diagram in event #1, the last cell sampling was "1",
so the trigger cell is "2". In event 2 (red case), the trigger cell is 5. If you would run like this, you see only the part of the waveform BEFORE |
Wed Nov 30 10:45:29 2016, Stefan Ritt, Long timing between two channels
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You cannot measure times longer than 1024/sampling rate.
Stefan
Randall |
Wed Nov 30 19:05:24 2016, Stefan Ritt, DRS4 Initiation
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Uhh, there are 1000 things which might be wrong. A bit like "my car is not working, it makes strange noise". Without having a look under the
hood, there is just some wild guessing:
- Is your ROFS input at the right value? Your O-OFS? |
Fri Dec 2 16:47:37 2016, Stefan Ritt, DRS4 Initiation
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No, I can't think of anything else. There is no intermediate addressing stage. The only thing which sometimes happens is that the QFN76 package is
not soldered correctly. If you don't have this under control, some pins might have a bad contact. You can check this by touching with a oscilloscope
probe not the PCB pads but really the pins from the side, which is a bit tricky. |
Fri Jan 13 13:16:09 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3
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The error probably comes from the fact that the drsosc.exe application is a 64-bit application and cannot be executed under XP any more. Unfortunately
XP is forbidden at our institute for security reasons, so I have no machine around where I could compile the executable fro XP. Another problem is the
libusb library used by drsosc.exe. Not sure if there is a XP version available any more. Have a look yourself at http://www.libusb.org/wiki/windows_backend |
Fri Jan 13 13:50:10 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3
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Can you try that executable under XP: https://www.dropbox.com/s/j1n09afhbmh0zzu/drsosc.exe?dl=0
Gregor
Kramberger wrote:
Hi all |
Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems
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In the evaluation board we use an ADCMP601 comparator, which has a setup and hold time of 4.6 ns. So a pulse which exceeds the threshold for less than
4.6 ns will not trigger the board. If you AND two signals together, an additional constraint might apply on the coincidence pulse. This is processed in
the FPGA, but once it becomes too short, it won't trigger the board as well. I never made a real measurement of that, but I would not be suprised if |
Tue Jan 31 08:40:04 2017, Stefan Ritt, LLD and ULD discriminations,
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Not inside the board. Each channel has a single discriminator. You can select to trigger on a rising or falling edge, but you don't have two levels.
What you can do however is to make an external trigger, like using old NIM logic. You can make discrimaiton with different levels and use a coincidence
unit to combine them. Then feed the trigger into the external trigger input of the evaluation board (5V TTL level, not NIM level!). |
Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl
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This is indeed currently not implemented. But there is a simple C program drs_exam.cpp, which connects to a board and safes some data. You could modify
that program to your needs.
Stefan |
Wed Apr 5 12:28:28 2017, Stefan Ritt, drscl doesn't find eval board but drsosc does (Windows 7)
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Two people report now this problem, while this works fine at our lab. So I'm puzzled right now.
I attach two screenshots from the device manager and the Command Line interface. Can you compare it with what you see? Which is the firmware
version of your evaluaiton board? |
Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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You have to download the package for your board, which then includes also the correct firmware for your board. If you have a V4 board, your firmware
is in drs-4.0.2.tar.gz which you can download from Dropbox at https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Martin |
Mon Apr 10 10:50:57 2017, Stefan Ritt, drs4 registers behaviour
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Using the RESET line to reset registers is not a good idea since it can have some bad side-effects. The READ SHIFT register is NOT affected by RESET,
so you have to inititialize these registers differently. To set a "1"-value at a defined position, you have to follow figure 11 in the data sheet.
Once you executed that, your "1" is always at the same posiiton (namely cell #0), so after 1024 clock cycles you arrive at the same state, and |
Mon Apr 10 14:05:17 2017, Stefan Ritt, drs4 registers behaviour
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1. WRITE SHIFT register and CONFIG registers are initialized to "1" on power up, but if you want to change that, use A0-A3 etc. as you indicated.
2. If you address the READ SHIFT register by applyin "1011" to A0-A3, the input of the register is connected to SRIN. So in fig. 11,
you apply 1023x"0" plus 1x"1", which effectively clears the register and keeps one "1" at the last position, so on the next |
Tue Apr 11 09:41:44 2017, Stefan Ritt, drs4 registers behaviour
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What I do is the following: Have the RESET input unconnected. When you power up, this makes an internal reset during the power up, and that's all
you need. Then configure your registers using the sequences described in the manual. Then do not touch the RESET any more.
Stefan |
Thu Apr 13 16:50:18 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Hard to say. Timing calibration is quite delicate. If you start from scratch, better read this paper: https://arxiv.org/abs/1405.4975
If you try to extract the code from DRS.cpp, better read the paper, too. Probably it will not be possible to develop or extract the code without
knowing how it works. |
Thu Apr 13 17:02:01 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Than you can try to isolate the code. Note that different SCAs might work differently. Like the DRS4 has a channel-to-channel jitter which others might
not. But you will see.
Stefan |
Wed Apr 19 12:17:25 2017, Stefan Ritt, Wave rotation during transfer from the board?
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This is correct. Actually the amplitude array is rotated already inside the DRS4 chip. So the readout starts with the stop cell plus one. If you do not
do anything, the waveform is already "rotated". If you want the waveform to start with physical cell #0, you have to "unrotate" it.
Stefan |
Tue May 23 10:24:47 2017, Stefan Ritt, Invalid magic number 0000
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Under linux, many people observed that the USB connection is unstable to the evaluation board. This must be related to the linux USB stack, since my
code runs fine under MacOSX and Windows, where I use the same USB library (libusb-1.0). So I can't do anything from my side. Baybe the linux system
has some tools to reset an USB endpoint. I googled it and found some proposals here: |
Fri May 26 08:48:25 2017, Stefan Ritt, Invalid magic number 0000
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There is no other way to reset the board. As I said, people running this under Windows or MacOS are fine, so maybe this calls for a change of OS.
Esperienza
Giove wrote:
Hello, thanks for your answer. Unluckily if i try to reset in this |
Tue May 30 21:00:26 2017, Stefan Ritt, Setting input range
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See elog:531
Esperienza
Giove wrote:
Hello, |
Thu Jun 8 15:52:20 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?
Stefan
Rebecca |
Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Hi,
from our screenshots I see the following:
- you have sometimes a huge oscillation in your preamplifier. Fix this first before doing any waveform recording |
Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND)
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Unfortunately not with the current firmware.
Stefan
Esperienza |
Wed Jul 12 20:16:05 2017, Stefan Ritt, Time resolution between boards
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Yes this should be possible.
Stefan
Toshihiro |
Mon Oct 2 16:08:05 2017, Stefan Ritt, Event acquisition pace for irregular timing
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As written in the documentation, the DRS evaluaiton board has a maximum trigger capability of ~500 Hz. This is limited by the USB bus which has a finite
data transfer rate. If you build your own electronics around the chip (like many other groups are doing), you can squeeze this to a few kHz, but it is
some development effort. |
Mon Oct 16 15:35:22 2017, Stefan Ritt, Raspberry Pi Connection Failure
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Have you tried as root? Maybe you miss some permissions.
Stefan
Jonathan |
Wed Oct 18 09:12:26 2017, Stefan Ritt, Time offset
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No this is not possible. But you can delay your signal externally (like with a delay cable or electronically) and then send the dealyed signal to the
evaluation board for triggering.
Stefan |
Fri Nov 3 13:28:04 2017, Stefan Ritt, Triggering using AND
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Think about: How would you make a coincidence (AND) between two edges? Since an edge is infinitesimally small, there is no way to make a meaningful coincidence
between edges. Therefore, the DRS4 EB firmware makes a simple AND of levels. If you trigger on rising signals and do an AND, then you get a trigger if
both values are above their threshold. For falling edge trigger (arrow goes down in the trigger configuration) the board triggers when both signals are |
Wed Nov 22 08:48:36 2017, Stefan Ritt, using of the DRS Command Line Interface
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The command line interface is more a debugging tool for experts, and you are not supposed to use it except to test the connection to the evaluation board.
The programs for the user are the DRS Oscilloscope and the drs_exam.cpp example program to read out the board with your own program.
Stefan |
Wed Nov 22 09:14:18 2017, Stefan Ritt, using of the DRS Command Line Interface
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Remove the check mark from the "Lock" box and enter a different value in the sampling speed box and hit return.
chen
wenjun wrote:
OK!Thank you! One more question,when I use the Oscillocope ,I found |
Wed Nov 22 14:52:31 2017, Stefan Ritt, Averaging capabilities
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This feature is not yet implemented. The (disabled) software swtich is more like a kind of a reminder to myself to work on that one day...
Diego
Yankelevich wrote:
The Display window in the Oscilloscope software shows averaging |
Tue Dec 12 13:58:06 2017, Stefan Ritt, External trigger using Raspberry Pi
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Indeed the code does not work for the current evaluation board, it has been written for a previous version and never been updated. Please use following
code to enable the external trigger
/* use following lines to enable the external trigger */ |
Wed Dec 20 16:21:42 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp
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First you need a board which is modified in hardware to support channel cascading. Basically there are internal resistors which connect each input connector
to two channels. You have to specify this when you order the board. Then you can use the new drs_exam_2048.cpp file contains in the git repository which
correctly configures and reads out the board in two-channel cascading mode. Putting all 8 channels together is not supported by the evaluation boards. |
Wed Dec 20 22:14:35 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp
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https://bitbucket.org/ritt/drs4eb
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Wed Jan 17 10:09:09 2018, Stefan Ritt, The input signals recorded are different with the signal showed in oscilloscope
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First thing is to do another voltage calibration. Disconnect input, "Config", "Execute Voltage Calibration". If this does not fix
the problem, the board is probably broken. This can happen if you send very high input singals to the board (like >10V) and exceed the maximul allowed
limit from the datasheet. In that case the board needs to be repaired. Please contact me directly (via email) so that we can make you a quote. |
Thu Jan 25 08:00:16 2018, Stefan Ritt, problem with the drscl(drs507)
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This problem has been reported by several people, like elog:551
So far I could not solve it. On the computers at our lab it works find so I cannot reproduce and fix the problem. One suspicion I have is that
the underlying libusb library needs to be updated. You can try to install the newest version from their website at http://libusb.info/, but I haven't |
Tue Feb 27 13:29:47 2018, Stefan Ritt, WIndows Connection problem with drs507 SOLVED
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Dear Steven, many thanks for this information, this is very useful. I know of people having problems on Windows 10, maybe this will also help them.
Stefan
Steven |
Tue Feb 27 17:04:12 2018, Stefan Ritt, DRS4 Dead times
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XML is very slow to write, and you are probably limited by that. Switch to binary mode, which is much faster. You will see in the end a maximum rate
of ~500 Hz, and thus a dead time of 2ms, independent of the sampling speed. Note that you have only an evaluation board, which is optimized for ease of
use. If you develop your own electronics, and do optimized readout, you can bring the deadtime down to 30ns x number of samples + 2us, or 32us if you read |
Tue Feb 27 18:12:32 2018, Stefan Ritt, DRS4 Dead times
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For applications which are critical on the dead time, one typically uses one ADC per DRS4 channel, and thus the dead time stays at 32us. If you multiplex
two DRS4 channels into one ADC channel, then it goes to 32us.
Stefan |
Fri Mar 2 20:17:17 2018, Stefan Ritt, ROI
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N'/N is correct. The 2 us "from the response you got from me" come from the fact that after readout, you have to start the DRS4 again.
During this time, the power supply usually becomes slightly unstable, and it takes on the evaluation board about 2us to stabilize it again. Tha't why
I add the 2 us. If you don't care about slight offset effect, or if you make a better power supply, you dead time would be 10*30ns = 300ns for 10 samples. |
Thu Mar 15 08:44:26 2018, Stefan Ritt, sub-ms precision timestamps?
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Putting sub-ms precision into the header does not make sense, since the USB transfer only happens in time-slots of about 2 ms. To get better timing,
you would need a hardware time clock in the FPGA, which does not exist right now.
Best, |
Fri Mar 16 14:00:06 2018, Stefan Ritt, confusion about the description in drs.cpp
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The FPGA is very small, so it only has an address space of 256 bytes. Look at the definition in DRS.cpp
#define USB_CTRL_OFFSET
0x00 /* all registers 32 bit */ |
Mon Mar 19 15:12:02 2018, Stefan Ritt, Running drs_example.cpp
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The time channel is already calibrated in ns. So for 5 GSPS, the time scale goes from zero to 200. Concerning your other issues I will come back to you
later.
Stefan |
Mon Mar 19 16:22:42 2018, Stefan Ritt, ROI
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The DRS4 has an internal storage of 1024 capacitors. They work as a ring buffer, so at 5GSPS you can store 200ns wide signals. After 200ns, the first
samples are overwritten by new samples, so you always have the last 200ns of samples stored. Once you trigger the DRS4, this buffer is frozen, and the
readout of this buffer causes the dead time. No trigger, no dead time. Hope this answers your question. |
Fri Mar 23 09:39:55 2018, Stefan Ritt, Read the CalibrateWaveform
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You don't have to read and calibrate the waveforms in your user code, but can rely on the DRS.cpp library to do that. Just look at the drs_exam.cpp
program coming with the distribution. It uses the function b->GetWave() to retrieve the calibrated waveform. If you like, you can look into that function
to learn how to apply the calibration, but I can tell you that it's a bit complicated. Since each event starts at an arbitrary stop cell in the DRS4, |
Tue Apr 17 13:28:23 2018, Stefan Ritt, DRS4 read_binary.cpp
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On the software download page at https://www.psi.ch/drs/software-download you find a link to all versions of the DRS software, which is located
at: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Earch .tar.gz file has a date, which should help you find the correct version. |
Wed May 2 09:24:53 2018, Stefan Ritt, DRS4 using drs_exam.cpp to save as binary files
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You have to write the C/C++ code yourself to write data in binary or any other format. All information is present after the waveform readout in drs_exam.cpp,
so it's just a matter of proper write() functions. Please consult any C/C++ handbook on how to write to files.
Hyunseong |
Wed May 2 12:12:42 2018, Stefan Ritt, Peak at 0 mV in traces
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I note that your peak at zero is exactly twice as high as the bins left and right, so this looks to me like a binning problem in your histogramming.
Maybe your bin #0 goes from -1mV to +1mV, which all other bins are just 1mW wide. Can you check that?
Stefan |
Fri May 4 11:35:20 2018, Stefan Ritt, Peak at 0 mV in traces
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I tried the following:
- trigger on a 10 MHz sine wave on CH0, CH1 was open
- run drs_exam.cpp program and write data.txt with a few events |
Fri May 4 11:56:08 2018, Stefan Ritt, Voltage and Timing Calibration in drs_exam.cpp
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Have you set the sampling frequency
b->SetFrequency(5, true);
before the calibration? |
Fri May 4 12:11:57 2018, Stefan Ritt, Running drs_example.cpp
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And here is the second part of your answer: When you change the input range, you have to redo the voltage calibration. Best is if you do that in the
DRSOsc program, then you see that it's working. Then start your custom program and use the same range.
Stefan |
Sun May 6 11:45:09 2018, Stefan Ritt, confusion about the description in drs.cpp
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The locbus_addr is indeed 32 bits wide, since the firmware was originally derived from some firmware running in a VME crate, and the VME bus has 32 bits
or addressing. So you will still find some "historic" remnants from that era. In the USB firmware, lcobus_addr[32:8] is always zero. Sorry for
the confusuion. |
Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces
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The DRS chip is read out with a 12 bit ADC, thus the phyical resolution is roughly 1V/4096 = 0.24 mV. I say roughly since the DRS has an analog gain
of 0.98, which is corrected for. Now you have integer values which are converted into floating point numbers my multiplying them with ~0.24mV. If you then
do histogramming with different bin sizes such as 0.1 mV and 0.35 mV , you get aliasing effects. The code truncates the result to 0.1 mV, which can give |
Wed May 9 09:03:52 2018, Stefan Ritt, Manual Rev5.1 Figure 1, optional components
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I updated the picture in the manual with a current picture of a Rev5.1 board, and also added a picture of the bottom side. If you need a picture without
the blue labels, have a look at https://www.psi.ch/drs/old-evaluation-boards at the bottom.
Here is the explanation of the optional components: |
Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
Fri Jun 8 08:11:05 2018, Stefan Ritt,
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Several people reported this problem, but we cannot reproduce it at our lab. Both the oscilloscope and the command line interface use exactly the same
code to connect to the board. Have you tried the solution reported here: elog:657 ?
Best, |
Wed Jun 13 13:42:47 2018, Stefan Ritt, Maximum analog input voltage
|
In principle the numbers in the manual are correct. But they relate to pulses of a certain length, because the input protection only works for DC voltage
and for pulses which are not too long. Since we could not write this all on the label of the board, we decided to put there 100% safe value as a "warning"
to people, meaning that if pulses are above 2.5V, they should look into the manual and read the details. |
Tue Jun 19 10:05:50 2018, Stefan Ritt, The data acquisition speed
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How do you tigger the board? In your code below you start the board (StartDomino()) and then wait for a trigger. Setting the trigger level to zero (via
SetTriggerLevel(0)) is certainly wrong. Please have a look at drs_exam.cpp in the distribution and use the same functions used there. If you want to trigger
the board, you need some external pulser with high enough rate (more than 500 Hz or course). You can also "software" trigger the board with a |
Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width
|
Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal
routing on the DRS4 chip.
Stefan |
Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support
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I put that on the wish list, but I won't have time for that in the next months.
Stefan
Martin |
Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed
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The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of
the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there
remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. |
Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
|
Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |
Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
|
The "Trigger OUT" has changed recently. It goes high on a new trigger, but then STAYS high until the board has been read out by the PC and
re-started. This allows better synchronization with some external trigger, which can be re-armed with the falling edge of the trigger out signal. The signal
can be quite long, since readout of an event via USB typically takes 2 ms, but can be more if the PC is busy. If you need back your 150 ns pulse, |
Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
|
In meantime I even updated the manual.
Stefan
Gerard |
Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?
|
The attenuator compensates for the gain of the buffer which is slightly above one. In addition, it serves as a "placeholder" in case one wants
larger input signals. One can easily convert the attenuator to -6db, -12db, etc. by chaning the resistors.
Stefan |
Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue
|
That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters,
which all have different propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins,
you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
|
Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
|
The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |
Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software
|
This one elog:361 should still work.
Stefan
Abaz |
Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s)
|
The reduction of rate is because you save in XML format, which is an ASCII format, so human readable, but takes long to write. If you switch to binary
format and write on a decent fast hard disk, you should get back to 450 Acq/s.
Stefan |
Mon Feb 4 16:46:04 2019, Stefan Ritt, Different Distances between the sampling points
|
The sampling points are NOT equidestant, they have varying bin widths of 150ps to 250ps at 5GS/s. That's due the way the DRS4 chip works. You might
have neglected that fact in the past, but that would have led to poor timing resolutions (typically 1-2ns resolution only). To get bins with the same width,
you have to treat your waveform as a real X/Y points (or better U/T), and the re-sample that cure, maybe spline-interpolated, at 200ps bins. |
Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points
|
elog:361
Hans
Steiger wrote:
Sorry.... but is there a solution or a Root Macro, that reads the |
Wed Feb 20 08:08:42 2019, Stefan Ritt, meg?
|
You have to change the path to libusb-1.0.lib to the one where you installed it.
Stefan
Lev |
Wed Feb 20 12:56:56 2019, Stefan Ritt, meg?
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No idea. Maye some access problem. Have you tried to start your program under an admin account?
Stefan
Lev |
Thu Feb 21 09:57:53 2019, Stefan Ritt, no board found
|
Could be. Have you tried that elog:657
Stefan
Lev |
Mon Feb 25 08:48:27 2019, Stefan Ritt, no board found
|
"dynamic" or "static" does not matter, as long as you don't use your program on another computer. I have no more idea about the
"no board found" problem. It works ok on all computers I tried at our lab.
Stefan |
Fri Apr 12 09:55:50 2019, Stefan Ritt, multi-board
|
Subtract 16 ns from your measured value ;-)
Stefan
Lev |
Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board
|
If you have two signal going through two cables, the cable have never the same length (on a scale of picoseconds), and you have to calibrate that anyway.
So a proper timing calibration is not a crutch.
What do you mean by "manual 50ps"? The manual does not mention any resolution. In my experience, you can achieve about 10ps between |
Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state
|
Dear Andrew,
the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately
the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline |
Wed Jun 26 13:08:42 2019, Stefan Ritt, drs_exam is always reading out a sin wave
|
Sure, that’s correct. The example program turns on the internal sine wave generator in case people don’t have a real signal. That’s
why it’s called „example“. Find the code which turns on the generator and change it. You will also have to change the trigger settings
depending on your actual signal. |
Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave
|
Actually in the original drs_exam.cpp the sine wave oscillator is turned off with this command
/* use following line to turn on the internal 100 MHz clock connected to all channels */
//b->EnableTcal(1); |
Mon Jul 15 17:26:50 2019, Stefan Ritt, Evaluation Board Test Functionality
|
Have you set the trigger correctly to the channel with your signal, polarity and level? Do you undersand the difference between normal and auto trigger?
Why don't you post a screendump. Are you ABSOLUTELY SURE that you have a signal on your cable? Have you tried with another oscilloscope? Are you sure
that your SMA connector is good? |
Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance
|
The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms
and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not
exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. |
Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance
|
The DRS4 input is high impedance. So if you like you can terminate it with 100 Ohm differentially and route it with 100 Ohm. But if you keep the lines
short, the reflection is negligible. That’s what we made on the evaluation board.
Ismael |
Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register?
|
Hi Bill,
you keep DENABLE active all the time to keep the Domino Wave running, but you deassert DWRITE if you change any register via SRCLK. There is
no shadow register, just a simple shift register, but with DWRITE being low, the domino circuitry does not touch it. |
Tue Aug 27 09:14:03 2019, Stefan Ritt, DRS4
|
Is a 5 GSPS oscilloscope suitable for use with Silicon surface barier detectors?
chinmay
basu wrote:
Is DRS4 suitable for use with Silicon surface barrier detectors? |
Mon Oct 14 10:14:46 2019, Stefan Ritt, how to acquire the stop position with channel cascading
|
You first set A3-A0, on the next clock cycle you issue pulses on srclk, and about 10ns after each clock pulse the output shows up at srout. Best is to
verity this with an oscilloscope.
The radout of the shift register is independent of the readout mode, so you can use with with MUXOUT as well. |
Mon Oct 14 12:56:13 2019, Stefan Ritt, how to acquire the stop position with channel cascading
|
Note that you have to read out the Write Shift Register only if you do channel cascading, e.g. configuring the chip with 4x2048 bins by setting the Write
Shift Register to 01010101b. Then the Write Shift Register tells you in which 1024-bin segment the Domino Wave has been stopped. If you use the normal
8x1024 bin mode, you don't have to read out the Write Shift Register since it continas only 1's. |
Mon Oct 14 15:27:09 2019, Stefan Ritt, how to acquire the stop position with channel cascading
|
If you configure the Write Shift Register with 01010101b, then all you have to do after a trigger is to set A3-A0 to 1101. The WSROUT pin shows you then
either ther state 01010101b or 10101010b, you the pin should be 1 or 0, and that's all you need. The Write Shift Register is NOT routed to the SROUT
pin, you only see it at the WSROUT pin. |
Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0?
|
t0,0 refers to the time of cell #0 of channel #0. So basically you keep channel 0 fixed, calculate the difference of each channel's cell #0 in respect
to channel 0, and align all channels except channel 0 so that their cell #0 has the same value. There is an inconsistency between the channel numbering.
The formula uses 0...3 and the manual says "channel 1" but it means actually the first channel, which uses index "0". |
Fri May 22 12:53:33 2020, Stefan Ritt, DRS4 Evaluation board control tool 'drscl' with macro file
|
There is an example program in the distribution under software/drscl/drs_exam.cpp which is a stand-alone program to do what you need. It uses the C library
coming with the distribution. It configureres the board, defines a trigger, and then writes a few waveforms into a file. You can use it as a starting point
for your development. If you need any other language, you have to develop bindings to the C library. |
Fri May 22 13:24:51 2020, Stefan Ritt, Type check at DOFrame.h in official software
|
The software is a bit outdated, I will soon make a new release.
In meantime, you can replace that like with
bool GetRefclk(int board) { return m_refClk[board]; } |
Tue May 26 12:44:16 2020, Stefan Ritt, Domino wave
|
Look at the attached picture. For simplicity, only 4 cells are open and tracking the input signal. Time is flowing from top to bottom. So initially,
a train of 4 cells is open. When it's stopped, the train stops not immediately, but kind of "runs against a wall" at the stop cell. So each
cell is open for four time ticks effectively, and you can use all 1024 cells. |
Mon Aug 31 10:52:42 2020, Stefan Ritt, Dynamic Range Evaluation Board and Software
|
You cannot go below -0.5V for the inputs, since the board does not have an internal negative power supply, which would be necessary for that. If you
have -0.8V pulses, the easiest is to use a passive inverter at the input to convert it to a 0.8V pulse.
Stefan |
Mon Aug 31 17:17:30 2020, Stefan Ritt, Channel Cascading
|
If you have a board with cascading option, it should show the "combined" option in the 2048-bin option enabled (not grayed), as in the
attached screen shot. If the 2048-bin option is all greyed out, the system does not recognize the cascading option. If your board has a sticker "2048
bin" and you still see the 2048-bin option greyed out, it might mean that a resistor on that board has been forgotten. If you do not see the "2048 |
Wed Oct 7 10:56:03 2020, Stefan Ritt, External triggering
|
The trigger is there only to trigger the chip, but cannot be used as a precise time reference. If you want to measure precise timing, do this always
BETWEEN two inputs, never between an input and the trigger. You might want to split and delay your trigger signal and feed one copy to another input of
the evaluation board as your reference. |
Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register
|
Dear Seiya,
1) That's correct. SRIN is ampled at the falling edge. Pleae make sure to obey the hold-time as written in the datasheet. P.12, Fig. 11:
SRIN must be stable before the falling edge of SRCLK and tH after the falling clock. tH is 5ns according to table 1. |
Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register
|
This is a static shift register, so you can make the clock as slow as you want. Actually I don't use a "clock", I just use a data pin I
control via a state machine in the VHDL code. This way I have more control over the edges. I need several (internal) clock cycles to produce one SRCLK
clock cycle, but that does not matter for the DRS. |
Thu Dec 17 11:31:34 2020, Stefan Ritt, drs sources on github?
|
Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/
But development kind of stalled, so there will be updates only in case of severe bugs, which are kind of gone after 10 years now.
|
Wed Jan 20 17:37:51 2021, Stefan Ritt, drs4 persistence
|
The chip itself can only sample a single waveform, that must be done in the attached software. The current DRSOscilloscope software coming with the evaluation
board has not yet implemented that, but if you write your own software you can do so.
Taegyu |
Fri Feb 26 08:52:50 2021, Stefan Ritt, DRS spike removal for multiple waveforms
|
Just look at the definition of the function below, all parameters are explained there. In meantime we have a firmware fix to avoid the spikes inside
the chip, but I have not yet found time to update the evaluation board.
Stefan |
Fri Feb 26 17:59:14 2021, Stefan Ritt, Trouble getting PLL to lock
|
I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!
There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some
ideas: |
Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock
|
Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?
Tom
Schneider wrote:
Stefan, |
Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock
|
Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB
trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2
is not really working. |
Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock
|
That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros
into the config register, thus disabling the PLL. Shame that I haven't thought of this before.
Stefan |
Wed Apr 7 08:26:12 2021, Stefan Ritt, Unexpected noise in muxout: t_samp related?
|
Dear Sean,
noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below
1 mV if the DRS4 input is clean (try to short it). |
Fri Apr 9 20:55:28 2021, Stefan Ritt, Unexpected noise in muxout: t_samp related?
|
If you do the cell calibration correctly, your noise should be ~0.4 mV. You seem to be 2-3x larger. The periodic negative spikes come if you dont'
sample at the right time. Adjust t_samp until they are gone.
Stefan |
Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings?
|
elog:824
Sean
Quinn wrote:
Dear DRS4 team, |
Wed May 5 10:12:44 2021, Stefan Ritt, recording only timestamp and amplitude and/or filesize maximum
|
The maximum file size depends on the underlying linux file system. Common values are 4-16 GBytes.
Stefan
Abaz |
Mon Aug 9 12:50:31 2021, Stefan Ritt, C code to read the 4 channel with external trigger
|
Sorry the late reply, I was on vacation.
Here are some answers:
1. I'm sorry I can't help much here, since I currently don't have a Windows 10 computer here to compile any code. I moved now completely |
Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading
|
The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what
could be wrong:
Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern |
Sat Sep 18 15:48:30 2021, Stefan Ritt, drs_exam_multi with non-v4 boards, default configuration
|
Hi,
please note the the evaluation board is what it says, a board to evaluate the chip, and is not meant for a full-blown shiny multi-board DAQ channel,
so support for that is kind of limited. |
Thu Oct 14 15:25:07 2021, Stefan Ritt, livetime (or deadtime) of DRS4 evaluation board
|
The one thing you can do easily is to look at the scaler values. If one channel counts all physical events, and you have all read out events, then the
ratio give you the live/deadtime. The hardware scalers also keep running during the DRS readout.
Stefan |
Thu Oct 14 18:42:31 2021, Stefan Ritt, livetime (or deadtime) of DRS4 evaluation board
|
I would say not exactly, but it's a good approximation.
Keita
Mizukoshi wrote:
Thank you very much for your response. |
Tue Oct 26 12:00:51 2021, Stefan Ritt, External trigger and drs_exam
|
1. Why should your waveform start from 0 to 5ns? I don't get your point. Whenever you trigger a readout, you get a 200ns wide time window, and by
definition it starts at zero.
2. In the software distribution you have a drs_exam_2048.cpp program. Note that your board needs to be physically modified before delivery to |
Tue Oct 26 12:02:56 2021, Stefan Ritt, Trigger multiple boards independently
|
Unfortunately an independent operation from a single computer is not supported by the software. You can try to modify the drs_exam program and extend
it. You can poll all boards in sequence and just read out that one which got a trigger, then start the loop again. But I don't know how good you are
in programming. I needs a bit of experience to do that. |
Wed Oct 27 08:11:42 2021, Stefan Ritt, Trigger multiple boards independently
|
I'm not sure if the rate would go up to 2 kHz (not 2 GHz!). Depends how the USB hub is designed. What you can do however is to buy 4 RaspberryPis
(total cost 150$) and run everythign in parallel. The evaluation boards works nicely with the Pi's.
Javier |
Tue Nov 16 08:51:14 2021, Stefan Ritt, V3 board, only one channel works, all components at each channel input working
|
A V3 boards is already 10 years old and out of warranty. The software has no configuration to turn channels off except the channel buttons on the main
page on top of the sliders. I presume the channels are broked due to some overvoltage applied to them (the V5 board is better protected against over voltage).
You can send it the board for repair, but it will cost almost the same amount of money than buying a new boards. |
Mon Jan 3 17:13:41 2022, Stefan Ritt, DRS4 request assistance
|
1. fDOMINO is defined as fREFCLK * 2048
2. Good values can be derived from the evaluation board schematics: C1=4.7nF, C2=1nF, R=130 Ohm
3. A "1" means a logical high level. See Wikipedia: https://en.wikipedia.org/wiki/Logic_level |
Sat Jan 15 10:50:47 2022, Stefan Ritt, I want to know about the readout
|
student_riku
wrote:
Am I right in thinking that inputting 1 to DMODE (Bit0) in the configuration
register will connect the 1024th cell to the 1st cell? |
Tue Jan 25 14:34:42 2022, Stefan Ritt, Regarding measuring for a set time
|
drsosc is a graphical application contiously acquiring data from the board, and drscl is a command line tool for debugging, as written in the manual.
The drsosc application runs indefinitely, but I guess you refer to saving data (by hitting the "Save" button in the drsosc application).
Yes the save functionality has a number of events, since you cannot store data indefinitely, since your harddisk does not have indefinite space! |
Tue Feb 15 12:02:29 2022, Stefan Ritt, Cannot trigger on pulses, have to trigger on undershoot
|
The trigger comparator is a ADCMP601 unit which requires a minimum pulse width of 3-4 ns. I see that your pulses are only 1-2 ns wide. You have to make
your pulses wider in order to trigger on them.
Stefan |
Thu Mar 3 13:47:26 2022, Stefan Ritt, How to convert samples to volt?
|
The 'drscl' tool is more for experts, normal users are advised to use the DRSOsc oscilloscope.
The board has to be calibrated for a given sampling speed before calibrated data can be read out. Do that with the "calib" command,
specifying 5 for the sampling rate, 0 for the range (which is the middle between -0.5 and +0.5) and 1 for 1024 mode. If you then do "start", |
Thu Mar 3 16:14:16 2022, Stefan Ritt, Scaler issue to evaluate live time
|
The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50
Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV |
Mon Mar 7 08:45:32 2022, Stefan Ritt, Why does not trigger at higher sampling frequencies?
|
Unfortunately I have not idea what the problem could be. In principle the trigger should be independent of the sampling speed, since the trigger is only
made with a discriminator and a flip-flop. The hardware must be ok since you see the trigger with the oscillocope app. All you can do is to go through
the sorce code of the oscilloscope app, especially drsosc/Osic.cpp::ScanBoards(), SetTriggerLevel(), SetTriggerPolariy() etc. to make sure you do the same |
Mon Mar 7 16:37:54 2022, Stefan Ritt, Scaler issue to evaluate live time
|
I tried your measurement with the DRSOscilloscope app (see below), and I measure a constant difference of 10 Hz among the whole range of 100 Hz to 3
kHz.
So I don't know what's wrong on your side. Did you try with the oscilloscope app as well? Have you checked your pulse generator? The |
Sat Mar 12 10:13:24 2022, Stefan Ritt, Time calibration and the C++ API
|
DRSBoard::GetTime is declared in DRS.h line 720.
If you want to measure timing down to ps, you need some basic knowledge, especially about signal-to-noise and risetime. This cannot be taught
in a few sentenses, needs a full lecture. As a starting point please read that papat: |
Mon Mar 14 08:59:51 2022, Stefan Ritt, Time calibration and the C++ API
|
Looks like you have the some time calibration, not sure if it's the correct one. Sample the sine wave from the calibration clock, once with and once
without the timing calibration, then you will see if all points lie on a smooth line. Left: without timing calibration, right: with proper timing calibration:
|
Tue Apr 12 10:49:27 2022, Stefan Ritt,
|
A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works in our designs. Maybe double check the address lines with an oscilloscope.
Stefan
LynseyShun |
Fri Jul 29 14:09:35 2022, Stefan Ritt, Increase event rate, use ROI mode, and install sw from source in Mac
|
The firmware from the website always reads 1024 bins. You have to modify it to stop before that, like reading only 128 samples or so. For compiling under
MacOSX, this should work, since I do it myself.
Regards, |
Fri Jul 29 17:23:43 2022, Stefan Ritt, Spikes/noise sensitive to clock settings?
|
Look at the DRS4 data sheet, Figure 12. You see there the rising SRCLK pulse which outputs the next analog value. You also see tSAMP which describes
the sampling piont (strobe or clock sent to your ADC). The value of tSAMP must be such that the values is sampled at the point where it flattens out, just
2-3 ns BEFORE the next analog sample is clocked out, as written in the text. So you have to phase shift your clock going to SRCLK and the one going to |
Tue Sep 27 10:37:11 2022, Stefan Ritt, Required Firmware for DRS4 Evaluation Board Version 2.0
|
You find each software version at the usual download location at
https://www.dropbox.com/home/drs/drs4/distribution/Download/Linux
The one you need is probably drs-2.1.3.tar.gz which was the last version for the 2.0 board which is now more than 10 years old. |
Tue Sep 27 15:20:55 2022, Stefan Ritt, Required Firmware for DRS4 Evaluation Board Version 2.0
|
Sorry, got the wrong link. Here the right one: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
If you untar the archive, you will find a "firmware" subdirectory with all VHDL code.
Stefan |
Mon Oct 24 12:50:24 2022, Stefan Ritt, Channel Cascading Option in the 2048-bin
|
The board is delivered in one or the other mode and not meant to be changed by the user, since this requires very delicate soldering which is not easy.
If you try anyhow, you loose the quarantee. You can send the board back to the manufacturer for the modification, but this costs quite some moeny.
Best regards, |
Mon Feb 6 13:28:28 2023, Stefan Ritt, DRS4 installation via tar in ubuntu not working
|
I fixed the described error. Can you try the new version from https://bitbucket.org/ritt/drs4eb/commits/80b3af753ed32eb365725f0f3244a4109347c01b
Sebastian
Infante wrote:
Hello i cant install any the last versions that i downloaded from |
Mon Jun 12 14:22:04 2023, Stefan Ritt, Different sampling rates in multi-board configuration
|
No, that's unfortunately not possible.
Stefan
Javier |
Wed Sep 13 13:18:45 2023, Stefan Ritt, Input range switch added in Version 2.1.3
|
To achieve an input range of -1V to 0V, you need an external buffer which can shift this range into the DRS4 range of -0.5V to +0.5V. This external buffer
has then to operate with bipolar power supplies, like -2.5V to +2.5V, which are not present on the evaluation board.
Best regards, |
Wed Oct 25 19:47:23 2023, Stefan Ritt, WaveDREAM Design
|
No. This is a proprietary design.
Best,
Stefan |
Thu Feb 22 10:37:03 2024, Stefan Ritt, Simulation of FPGA
|
The Cypress has its own firmware, contained in the distribution under firmware/CY7C68013A/drs_eval.c. There you can see how the data is fetched. I kind
of forgot how exactly it worked, since I wrote that code back in 2011. But most if the Cypress code is just the configuration of the USB, the communication
with the FPGA is kind of straight forward in the Cypress implementation. But you have to read the manual of that chip to understand it. |
Wed Feb 29 06:46:47 2012, Sonal, DRS4- analog pulse counting
|
Stefan Ritt wrote:
|
Mon Apr 16 21:21:29 2018, Sobimpe Eniola, DRS4 read_binary.cpp
|
Hello everyone,
The new read_binary.cpp code
I will be very glad if anyone can help with the old version of read_binary.cpp code. The latest version I saw online was updated on June |
Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ
|
Hi,
I'm currently working on a little DAQ system with four DRS evaluation boards. Do i need to apply any specific settings when using the clock in/out
connectors for synchronization? I do not see anything like that in the drs_exam_multi example. |
Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ
|
Stefan Ritt wrote:
|
Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ
|
Hi Stefan,
do you know how these numbers (400ps and 60ps) scale with the sampling rate? The manual says they are for 5GS/s, do they change with slower sampling?
Thanks and best regards, |
Fri Oct 28 15:02:18 2016, Simon Mendisch, Problems with DRS command line
|
[quote="Stefan Ritt"]
You are the first one describing this problem (out of ~200 people), so I guess the problem must be on your side. Have you made sure to start the DRS oscilloscope
and the Command Line Interface not at the same time? Only one program can access the board at a given time. Have you tried disconnecting and re-connecting |
Tue Jun 25 23:04:29 2019, Si Xie, drs_exam is always reading out a sin wave
|
We are using the drs_exam.cpp to read out waveforms, but it seems to be outputting only sin waves on all channels - as if it was reading out the simulated
waveform from the oscilloscope program if we run it without the board plugged in. Does anyone know what is causing this?
We are taking data with a pulser plugged into channel 1, which produces a single pulse with width of 8ns, and nothing plugged into channel |
Wed Jun 26 15:10:09 2019, Si Xie, drs_exam is always reading out a sin wave
|
I see. Where is the code that we can use to turn off the generator? I thought the example is taking data with CH1 as the trigger.
For our board, which is BoardType == 9, it is running these lines:
b->EnableTrigger(1, 0); // enable hardware trigger |
Wed Jun 26 15:17:51 2019, Si Xie, Running drs_example.cpp
|
Hi Rodrigo, I'm wondering how you solved your original triggering problem. We are also having trouble with collecting data continously using the
example. Thanks.
Rodrigo |
Wed Oct 21 15:03:13 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register
|
Dear Stefan,
I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register. |
Tue Oct 27 15:02:09 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register
|
Dear Stefan,
Thank you for your reply. |
Wed Oct 28 04:32:19 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register
|
Dear Stefan,
OK, it's good to hear! Thank you! |
Mon Oct 17 16:29:37 2022, Sebastian Infante, DRS4 installation via tar in ubuntu not working
|
Hello i cant install any the last versions that i downloaded from the dropbox, i can untar the file called drs-5.0.6 and when i type "make"
while inside the extracted folder that starts working properly till a point and i get an error, its worth mention that i installed wxWidgets and could
make a simple hello world that worked properly in wxWidgets. |
Tue May 8 23:58:35 2018, Sean Quinn, Manual Rev5.1 Figure 1, optional components
|
Dear All,
I'm troubleshooting a board which uses the DRS4 and adopts an analog front end very similar to the evaluation board. As a result, we rely |
Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed
|
Dear DRS4 team,
On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance
achieved at 33 MHz. |
Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?
|
Dear DRS4 team,
I am curious about this part of the circuit: |
Wed Apr 7 03:29:39 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?
|
Dear DRS4 team,
I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are
several items to address in the post. |
Fri Apr 9 20:22:13 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?
|
Hi Stefan,
Thanks much for the quick reply. Ok, yes, things do seem ok after the offset calibration. I am running into some other issues I could use your |
Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings?
|
Dear DRS4 team,
I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy
data (post-calibration) with periodic spikes. |
Fri Apr 9 21:56:54 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?
|
Yes, there is some systematic board noise on this prototype, unfortunately
Ok, then it seems the other post I made might still belong in this thread after all. |
Thu Nov 14 11:39:06 2013, Schablo, Cascading of channels
|
Hello, I want use cascading of channels for 2048 cell - SetChannelConfig(0,8,4), but i can't understand how . Please, help me. Where i can
dowload 2048_mode.ppt. (I found information about this file in DRS.cpp (3445 line "/ combine |
Thu Nov 21 14:35:57 2013, Schablo, Cascading of channels
|
Stefan Ritt wrote:
|
Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
|
We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Problιme de Calibration de la DRS4
|
Bonjour, Je suis en stage dans un laboratoire ou on utilise pour echantillonnage des données, une cartes DRS4 5GSPS avec 1024 cell, mon probléme
réside dans la partie Calibration en tension selon l'article "Novel Calibration Method for Switched Capacitor Arrays Enables Time
Measurements with Sub-Picosecond Resolution". |
Sat Feb 19 17:25:29 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards
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Dear sir,
We have two evaluation boards of DRS4. We would like to use 8 inputs to be recorded on a trigger and we would like to find the relative time difference
of inputs. So is it possible to synchronize the sampling frequency of the two evaluation boards. |
Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards
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Stefan Ritt wrote:
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Mon Feb 15 19:43:34 2010, Ron Grazioso, Problem reading oscilloscope binary waveform output
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I have saved some waveforms using the oscilloscope application in both binary and xml. I can see that the xml file gives me proper data values
but when I try to read the binary file using IDL, it does not seem correct. This is a screen shot of the pulse I saved: |
Thu Apr 10 14:45:12 2014, Roman Gredig, DRS4 Evalboard V5 with Windows7Pro64bit
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Dear Stefan
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Thu Jun 12 12:40:03 2014, Roman Gredig, DRS eval bord v5 Timing
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Dear Stefan
I have two questions concerning the best time resolution with the DRS V5 eval board.
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Wed Aug 13 20:17:19 2014, Roman Gredig, binary files time calibration header in drs-5.0.2
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Dear Stefan
I have a problem considering binary data files.
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Tue Aug 26 14:16:26 2014, Roman Gredig, binary files with more than 4 drs board ver. 5.0.2
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Dear Stefan
after having some problems with writing binary files with more than 4 drs boards (in multiboard-mode) I might
|
Wed Mar 7 22:49:38 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp
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Hello,
We have been using the DRS4 evaluation board (S/N 2636) that works with the scope application. However we are trying to run the DRS4 evaluation
board remotely by modifying the drs_exam.cpp to acquire and store data continuously. |
Thu Mar 8 22:54:20 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp
|
We found a way to solve the previous problem, but right now when we try to set the input range only -0.5 to 0.5 is working. When we set the function
"SetInputRange(0.5)" for 0 to 1V the output is all zeros and with "SetInputRange(0.45)" we just get all the outputs -49.9mV.
What does that means? How to fix? |
Thu Feb 22 01:21:11 2024, Rod McInnis, Simulation of FPGA
|
Hello:
A bit of background: I am working on a project that is utilizing the DRS4 Evaluation board as a prototype platform for a dedicated, special
use capture. We will only be utilizing one channel of the ADC capture, and the 1024 samples is more than enough. |
Thu Nov 26 18:59:27 2015, Robert Adams, Saving histogram data
|
I would really love to be able to save histogram data, though I have not been able to do this. I could take a screenshot and extract the data from an
image, but would prefer to avoid this if there is a simpler way... possibly I have overlooked something obvious? Thanks very much for any advice or tips. |
Thu Jun 8 14:26:23 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
|
Hello,
I work with the DRS4 Evaluation Board V5 and I have a problem with the software.
I have a problem with |
Fri Jun 9 09:44:33 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
|
Hello,
It seems that a coincidence with two fixed channels suddenly works. I don't know why.
Screenshot 1 shows the trigger settings for the coincidence with two channels. |
Tue May 21 18:13:08 2024, Rebecca Hicks, Error when running drsosc
|
Hi, I'm a student trying to figure out the DRS4 board. I cloned the github repo, but when I run drsosc, I get an error: Gtk-Message: 10:06:38.376:
Failed to load module "canberra-gtk-module". I'm not sure what that means. The oscilloscope window does open up for me though. Thanks for
any help! |
Tue Jul 28 22:40:44 2020, Razvan Stefan Gornea, no board found
|
I have a very similar problem, the command line doesn't work but the oscilloscope program does! Tried to fix it using Zadig driver update. Using
Windows 7....
DRS command line tool, Revision 21435 |
Thu Jan 26 09:12:03 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting
|
Hello,
We are using DRS4 Rev.2.0 board.
We want to measure number of pulses generated by charge particle detector. These negative going analog pulses are very fast having rise time |
Thu Jan 26 09:44:34 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting
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Stefan Ritt wrote:
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Thu Jan 26 10:05:57 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting
|
Stefan Ritt wrote:
|
Mon Nov 28 22:28:34 2016, Randall Gladen, Long timing between two channels
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I don't believe I fully understand how the timing works between multiple channels on DRS4 board, even after reading the manual, but I am hoping to
measure a time difference between two channels longer than 1024/sampling rate. So far, I have written a program in Matlab to extract timing and voltage
information from the binary file to find the time difference between two channels that are set with the AND trigger logic and appear within approximately |
Fri Jan 16 13:29:05 2015, Rainer Hentges, Mac OSX Yosemite 10.10
|
Hello,
I can compile version 5.0.3 of DRS4sc on Mac OSX 10.0 without errors but when I want to execute the program I get the following error:
|
Mon Mar 7 13:38:03 2022, Radoslaw Marcinkowski, Problems with DRS4 Evaluation Board after Windows 10 upgrade - share of experiences
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Dear DRS4 Users,
I would like to share my expireinces with using of DRS4 Evaluation Board software (oscilloscope) after upgrade of Windows 10.
I had Windows 10 (Enterprise) in version from ~2016. It was working fine with DRS4 Scope software. Due to the company policy, Windows was upgraded |
Wed Sep 7 10:13:41 2022, Prajjalak Chattopadhyay, Register status after reset
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What are the default register statuses after DRS4 gets reset? |
Thu Mar 22 14:36:01 2018, Phan Van Chuan, Read the CalibrateWaveform
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Helo
I'm building an application for reading waveforms from the DRS4 board to PC. However, I am having problems reading calibration data from EEPROM
on DRS4 board. The calibration data is read through the function reference: |
Thu Jun 7 16:27:21 2018, Phan Van Chuan,
|
Dear Stefan,
I am using an DRS4 board to test the signal from an scintillator detector; It has connected well to the computer on DRS Oscilloscope (Figure
1). Now, I am having a problem of developing from the code of the drs_exam program, because the DRS4 board has not connected to the computer when translation |
Tue Jun 19 06:42:23 2018, Phan Van Chuan, The data acquisition speed
|
Dear Stefan,
We are using an DRS4 board V5.1 for building a metering system for the scintillator detector by a Labview program. The program was built based
on the functions in DRS.cpp and it reads data from channel 0 very well (Fig 1). Now, I am having a problem with the data acquisition from DRS4 board. The |
Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed
|
Thank Stefan Ritt, I added the SoftTrigger() just after StartDomino(), so now, The data acquisition speed the same speed as in the DRS oscilloscope.
I have misunderstood the "auto" trigger on an oscilloscope as setting SetTriggerLevel (0).
Thank so much! |
Sat Oct 22 13:24:20 2022, Phan Van Chuan, Channel Cascading Option in the 2048-bin
|
Dear Stefan,
We are using DRS4 evaluation board version 5.1 and firmware version 30000 (as the picture attached). Now, I am in need one channel with length 2048
bin. However, I can't find the resistors R99, ... ,R106 on the hardware of evaluation board; it seems my DRS4 evaluation board doesn't use 2048 |
Sun May 24 09:34:27 2015, Peter Steinberg, Peculiar behavior of time values for Rev5 DRS4 EB
|
Hi -
I am setting up a new DRS4 rev5 but using drivers and software we were recently using with a Rev4 (with a recent release of the drs4 code, from
mid-2014). |
Thu Sep 16 19:04:06 2021, Patrick Moriishi Freeman, drs_exam_multi with non-v4 boards, default configuration
|
Hello,
I made a modified version drs_exam_multi.cpp, but ran into an issue when running. When I ran it, it only found the two boards with
lower serial numbers (2781 and 2879) and complained that the others (2880 and 2881) were not v4. Would there be a simple workaround for this type of thing? |
Fri Jun 28 23:33:51 2024, Patricia Lecomti, Error when running drsosc
|
Salut !
Je vois que tu rencontres un petit problème avec ton installation. Le message "Gtk-Message: Failed to load module 'canberra-gtk-module'"
indique que ton système essaie de charger un module GTK spécifique qui n'est pas installé. Heureusement, ce n'est pas un problème |
Wed Mar 6 12:35:38 2013, Osip Lishilin, DRS4- analog pulse counting
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Hello, Stefan. Have you implemented pulse counting yet?
Best, Osip. |
Mon May 20 08:42:16 2013, Osip Lishilin, DRS4- analog pulse counting
|
Stefan Ritt wrote:
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Mon Jun 9 12:03:26 2014, Osip Lishilin, Announcement of new Evaluation Board V5
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Stefan Ritt wrote:
Hardware scalers for all four channels and the trigger working up to 200 MHz. With the trigger scaler |
Mon Jun 16 15:35:59 2014, Osip Lishilin, Announcement of new Evaluation Board V5
|
Stefan Ritt wrote:
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Fri Oct 12 14:06:04 2012, Moritz von Witzleben, DRS abbreviation
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Hello,
what is the abbreviation of DRS?
Thanks and kind Regards, |
Mon Nov 17 16:36:18 2014, Mickey Chiu, Raspberry Pi drsosc does not exit properly
|
When running drsosc on a raspberry pi, it seems the exit doesn't seem to work at all. This is true for the "exit" button on the window,
or the file menu exit, or the "x" on the window. I end up having to kill drsosc manually from the command line. This wouldn't be
such a bad thing except that it doesn't seem to store any settings when killed in this way. I'm wondering if anyone else sees the same thing, or |
Fri Dec 9 17:45:48 2011, Michael Bόker, Fixes to DOScreen.cpp for recent built on linux
|
> I was just building version 3.1.0 and ran into some problems in DOScreen.cpp. Basically the conversions from
> char* to wxString were generating "ambiguous overload" errors (in gcc 4.4.3, wx-2.8)
>
|
Tue Jun 16 20:45:54 2015, Michael Buadelk, DRS4 Evaluation Board Osc Application
|
Hi, I have a DRS4 v5 evaluation board and I have a novice question about the oscilliscop application. When I connect it to a photo-detector (silicon
photo-multiplier to be exact), the signal appears only on one half of the screen, and I cannot change it to be full screen, and pulse to be centered. I
tried changing delay time and played around with the settings of the applicaton but no success. I'd apprecite if someone help me on this, probably |
Sun Jun 12 08:45:52 2016, Michael, problems of DRS4
|
Hi
I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences
between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects. |
Sun Jun 12 08:49:54 2016, Michael, problems of DRS4
|
Hi
I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences
between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects. |
Wed Jul 14 14:55:09 2021, Mehrpad Monajem, C code to read the 4 channel with external trigger
|
Hi there,
Recently I bought a 5GSPS evaluation board with 2048 sampling points.
I want to read 4 inputs of the evaluation bord ar 5 GSPS or 2.5GSP and use an external trigger. |
Tue Aug 10 13:57:09 2021, Mehrpad Monajem, C code to read the 4 channel with external trigger
|
Thank you for the reply.
In the version that I have, I cannot find drs_exam_2048.cpp file. Could you please send me the link to download the software folder, which contain
this file. |
Tue Oct 26 10:41:46 2021, Mehrpad Monajem, External trigger and drs_exam
|
Hi Stefan,
I have two problems regarding using the drs_exam file with external trigger: |
Tue Oct 26 15:05:18 2021, Mehrpad Monajem, External trigger and drs_exam
|
Thanks for your reply.
1- I want to have a window size of 25.6ns instead of 200ns at 5GSPS. I have a 200khz high voltage pulser, which applies a pulse to my sample.
I want to digitize the detector signal for each pulse (each pulse has a 25.6ns period). The pulser and digitizer use same 200khz trigger signal from each |
Wed Aug 1 17:42:32 2012, Mayank S. Rajguru, Calculation of loop filter parameters (R,C1and C1) for 1 GHz
|
Hi,
we are planning to use the DRS4 in our board for 1 GHz sampling and digitization.
I have seen in the data sheet that "For the PLL to work, an external loop filter is required. This filter ensures quick locking and stable |
Thu Feb 25 17:56:39 2021, Matthias Plum, DRS spike removal for multiple waveforms
|
Hi,
Is there a way that someone can help me and my student to enable RemoveSymmetricSpikes function in the drs_exam.cpp? We are not 100% sure
how to call the function if you want to read out four waveforms. |
Sat Feb 12 13:06:56 2022, Matias Senger, Cannot trigger on pulses, have to trigger on undershoot
|
I am using the DRS4 board trying to measure pulses produced by an LGAD. I have no prior experience with this board, have just installed the `drsosc`
application and am exploring. I am experiencing some strange trigger behavior. Consider the following screenshot:
|
Wed Mar 2 17:25:10 2022, Matias Senger, How to convert samples to volt?
|
I am using the `drscl` app. My prior experience is practically zero, sorry if this is a very naive question. When I read using `read 0 1` (channel 0,
with calibration) I get this:
``` |
Sun Mar 6 17:54:47 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
|
I have connected 3 signals to the DRS4 Evaluation Board V5 which look like this in the drsosc app:
Note that here I am sampling at 5 GS/s. Using this app everything works perfect. |
Tue Mar 8 00:25:56 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
|
I have seen in the app that the trigger source buttons do something different than the "or" and "transparent trigger" buttons:
If I enable the setup from the right, i.e. OR in CH4 and "Enable Transparent Trigger" the app stops triggering. This is the configuration |
Tue Mar 8 12:20:00 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
|
Sorry for the spam. Just want to let you know that I was able to solve the problem, it was all due to a `float` being casted as `int` in the Python binding.
Now it works like a charm.
Matias |
Fri Mar 11 17:26:15 2022, Matias Senger, Time calibration and the C++ API
|
I am using the V5 board at a fixed sampling frequency. With the `drsosc` app I have executed the time calibration at 5 GS/s (actually 5.12 GS/s). This
is how my setup looks like in the app:
|
Sat Mar 12 16:52:36 2022, Matias Senger, Time calibration and the C++ API
|
Dear Stefan,
For the time of each bin I am using the values returend by `GetTime` without any assumption by my side. I did not notice before that the sampling
time is not uniform, but I see that this is already happening. This is an example plot from one of the signals I processed: |
Tue Mar 15 13:07:50 2022, Matias Senger, Time calibration and the C++ API
|
Thanks for your help. If I look into the app the behavior for the 4 channels is exactly as you show:
|
Tue Sep 5 03:28:52 2023, Matias Henriquez, Input range switch added in Version 2.1.3
|
Hello,
It is not quite clear to me yet how the input range is only determined by the front end and not the DRS4 chip. According to the datasheet, the
selection of ROFS determines whether the input differential range is -0.5V to 0.5V (ROFS=1.55V) or 0V to 1V (ROFS=1.05V) or -0.05V to 0.95V (ROFS=1.1V). |
Wed Jun 1 09:57:43 2011, Martin Petriska, Removing spikes
|
I have DSR4 eval board. Found that there are spikes in channels. Procedure Osc::RemoveSpikes to remove them looks litlle dificult. There is simple way,
if you doesnt need to measure all 4 channels.Spikes are in all channels, and it looks like they are same in time and value between channels. To remove
them, if you are not using one channel, substract that unused channel with spikes from used channel and your data will be without spikes. If you need all |
Tue Mar 20 16:23:33 2012, Martin Petriska, triger for measuring time between pulses in channels
|
I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is
version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger
on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold |
Wed Mar 21 09:33:00 2012, Martin Petriska, triger for measuring time between pulses in channels
|
Stefan Ritt wrote:
|
Mon Oct 29 18:30:28 2012, Martin Petriska, GetWave
|
I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) etc...is used. Is there primary (cell) calibration,
secondary calibration (Readout) and remove Spikes used, as in DRS Oscilloscope application? |
Thu Dec 6 09:23:36 2012, Martin Petriska, EVM rev4 board trigger change and drs_example
|
I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting for trigger (rev.3 is working). How to do in
drs_exam.cpp for example triggering on Ch0 && CH1 ?
Software 4.0.0, windows version. |
Wed Feb 13 16:58:40 2013, Martin Petriska, Nonuniform sampling
|
Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly sampled data?
Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga
Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel |
Tue May 21 13:32:13 2013, Martin Petriska, mac osx 10.6
|
> Hi,
>
> I would like to use the DRS4 with my macbook pro running osx 10.6.8.
|
Thu Jan 9 10:58:19 2014, Martin Petriska, v5 software with v4 board calibration
|
Hi
Question:
In v4 board, which channel has best calibration ? |
Thu Aug 21 11:03:36 2014, Martin Petriska, 10GSps on DRS4 Evm with delay cables
|
Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).
Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay
cable? |
Wed Aug 19 15:07:53 2015, Martin Petriska, QtPALS
|
There is software for DRS4 board and positron lifetime measurement availiable. Still in beta but works. Its usable for measuring time between
pulses in two or three channels and histogramming that time. (May be time of flight measurement should be tested too) Project code is here: http://sourceforge.net/projects/qtpals/.
More about it is here http://iopscience.iop.org/1742-6596/505/1/012044/. |
Tue Feb 16 11:55:54 2016, Martin Petriska, Saving histogram data
|
Robert
Adams wrote:
I would really love to be able to save histogram data, though I have |
Wed Apr 6 09:01:28 2016, Martin Petriska, DRS Oscilloscope freezing after a long run
|
Stefan
Ritt wrote:
I tried this night to run the board at a 10 Hz rate with an external |
Wed Apr 5 12:40:16 2017, Martin Petriska, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
|
I would like to implement fpga firmware changes for DRS4 eval board v4 to put there posibility for standard coincidence (for example to get triger
on two short (5ns pulses from Plastic scintilator) in 100ns coincidence window), Similar but more complex was done for eval v.5 boards ( https://forge.physik.rwth-aachen.de/projects/drs4-rwth
) Im beginner in state of FPGA design, but hope it will be not so dificult to implement same functionality in eval4 board. Is there any SVN server |
Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support
|
Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, but is it possible to add latch delay support to official firmware ? |
Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
|
Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed
|
Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
Wed May 11 04:01:14 2016, Maksat, DRS4 Macro to save events
|
Dear Stefan,
I am trying to setup DRS inside radiation enclosure and would like to write a simple script that will automatically save certain number of events.
Could you please point to me an example that can I use for Mac OS? I saw there is drs_exam.cpp in the directory but was not able to get work |
Tue Apr 12 10:40:36 2022, LynseyShun,
|
Hello, I am Lynsey. now I set A3-A0 to 1001 in ROI mode, but only OUT0 has output, and the other seven channels(OUT1-OUT7) do not output corresponding
waveforms.
In ROI mode, can OUT0-OUT7 output sampled waveforms at the same time? |
Thu Jun 16 05:31:25 2022, LynseyShun,
|
Thank you very much for your help!
Stefan
Ritt wrote:
A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works |
Fri Jun 24 09:57:36 2022, LynseyShun, Spikes/noise sensitive to clock settings?
|
Hello, I now have periodic spikes in CH0 and CH1 output. How can I eliminate these spikes? I'm sorry I didn't understand your elimination
method. Please explain the method in detail. Thank you very much
Stefan |
Thu Dec 23 03:42:26 2021, Lynsey, DRS4 request assistance
|
Dear Sir or Madam,
Good morning,I am using drs4 chip, and the measured fDTAP == 1/350ns, that is, fDOMINO == 1 / 350ns * 2048 == 5.8GHz.
I have three questions: |
Fri Dec 24 03:13:32 2021, Lynsey, Trouble getting PLL to lock
|
I also design the circuit myself. Our problem is the same. Can we communicate?
Stefan
Ritt wrote:
I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, |
Tue May 13 19:34:58 2014, Luka Pavelic, drsosc binary to cern ROOT file conversion
|
Hi,
Does anybody have program for conversion from binary or xml to cern ROOT *.root file? |
Tue May 13 22:03:47 2014, Luka Pavelic, drsosc binary to cern ROOT file conversion
|
Thank you for your fast and very helpful replay.
I made it work with drsosc version 4 but with version 5 i am getting weird results. Is it possible that they changed binary formatting? |
Wed Feb 20 08:03:04 2019, Lev Pavlov, meg?
|
Hey. Strange problem. Why does the compiler refer there at all? Library installed drsosc works
LINK : fatal error LNK1104: cannot open file "C:\meg\online\drivers\drs\libusb-1.0\libusb-1.0.lib" |
Wed Feb 20 12:13:44 2019, Lev Pavlov, meg?
|
Great, drs_exam compiles without problems. Now when you run the compiled file drs_exam writes board not found, but drsosc and drscl work without problems.
What could possibly be the matter?
thanks for your patience |
Thu Feb 21 09:51:24 2019, Lev Pavlov, no board found
|
Hey. Yes, the program is running as administrator. By the way, this is win10. Your drs_exam works fine. My drs_exam compiled wrote no board found. Maybe
this is a problem like in the post https://elog.psi.ch/elogs/DRS4+Forum/698. Maybe there were solutions to the problems?
Thank You |
Mon Feb 25 08:40:44 2019, Lev Pavlov, no board found
|
Hello. When compiling drs_exam, do you need to use a "static "version of usblib or a "dynamic" version?"The problem
with "no board found" is not solved. Thanks for your help. |
Fri Apr 12 09:39:30 2019, Lev Pavlov, multi-board
|
Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between
the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks |
Fri Apr 12 09:59:15 2019, Lev Pavlov, multi-board
|
I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what
is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but |
Fri Jun 16 17:34:20 2017, Laura Gonella, Driver installation on Windows 10
|
Hello,
I am trying to get a DRS4 board to run on Windows 10. I am having problems with the driver installation. I am getting the follwoing message
"There is no driver selected for the device information set or element" |
Wed Jan 6 15:51:58 2016, Larry Byars, Use of Channel Cascading in drs_exam.cpp
|
Hello Stefan,
Here in Rockford, TN we just got a new DRS4 evaluation board (Serail # 2612, Board Type 9, Firmware 21305) which is labeled as combined 2048.
It looks like the drs_exam.cpp only works with 1024 samples per channel. We'd like to be able to get 2048 samples from each of the four channels |
Tue Jan 12 15:42:31 2016, Larry Byars, Use of Channel Cascading in drs_exam.cpp
|
An update. I have been successful in making modifications to drs_exam.cpp so that I can get 2048 samples per channel.. The main changes were to the size
of the time_array and wave_array and adding a call to Set ChannelConfig(0,8,4). It was also necessary to change the parameters to GetWave so that the Trigger
Cell and WSR values were passed to get the channel combinations correct (2048 channel.ppt). |
Thu Apr 21 22:16:43 2016, Kyle Weinfurther, Negative fCellDT values from GetTimeCalibration()
|
Hello Stefan,
I am using four DRS4 v5 eval boards to digitize 16 channels of data. I have recently changed from saving the timing information of the waveform
using GetTime() to GetTimeCalibration(). When changing over, I noticed that some values for fCellDT for cell 498 are negative. Over the 16 channels used, |
Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime()
|
Hello,
I have a question about the GetTime() method in DRS.cpp. I understand how the DT values are applied for all channels, and I also understand
from the evaluation board manual that the timing of each channel is synchronized at sample 0, so samples should really be aligned from channel-to-channel |
Tue Sep 27 10:17:58 2022, Kunal Shinde, Required Firmware for DRS4 Evaluation Board Version 2.0
|
Hi, I am working on an old DRS4 board Version "2.0" with firmware revision "13191", I was unable to find this specific firmware source
files ("VHDL source code"), please help me where could I find this or send me the required.
Regards, |
Tue Sep 27 10:52:41 2022, Kunal Shinde, Required Firmware for DRS4 Evaluation Board Version 2.0
|
I checked the link you provided but it seems that the link doesnt exist please send me valid one.
Regards,
Kunal |
Fri Apr 15 12:58:46 2016, Konstantin Gusev, DRS4 purchase information
|
Hi,
I can't contact with Anita Van Loon about DSR4 chip's price and delivery.
Did you still sell it? Can you provide me this information? |
Thu May 21 07:18:48 2020, Keita Mizukoshi, DRS4 Evaluation board control tool 'drscl' with macro file
|
Dear experts,
I would like to use DRS4 evaluation board as DAQ system for small, table-top experiment. |
Thu May 21 07:38:05 2020, Keita Mizukoshi, Type check at DOFrame.h in official software
|
Hi,
I've failured to compile official software. The cause is the following line. |
Mon May 25 03:36:12 2020, Keita Mizukoshi, DRS4 Evaluation board control tool 'drscl' with macro file
|
Thank you very much. That is what I wanted.
Stefan
Ritt wrote:
There is an example program in the distribution under software/drscl/drs_exam.cpp |
Thu Oct 14 15:19:00 2021, Keita Mizukoshi, livetime (or deadtime) of DRS4 evaluation board
|
Dear experts,
I would like to use the DRS4 evaluation board for actual physics experiment. |
Thu Oct 14 18:03:52 2021, Keita Mizukoshi, livetime (or deadtime) of DRS4 evaluation board
|
Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the hardware scaler value is M, the livetime is realtime*(N/M). Is this correct? |
Fri Oct 15 06:15:53 2021, Keita Mizukoshi, livetime (or deadtime) of DRS4 evaluation board
|
Thank you very much.
Stefan
Ritt wrote:
I would say not exactly, but it's a good approximation. |
Tue Mar 1 19:03:37 2022, Keita Mizukoshi, Scaler issue to evaluate live time
|
Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger. |
Fri Mar 4 03:55:33 2022, Keita Mizukoshi, Scaler issue to evaluate live time
|
Thank you very much for your explanation.
I would like to show you a pulse example ('black line is the threshold). |
Sun Apr 5 22:16:48 2015, Julien Wulf, DRS4 Evaluation Board Baseline/Voltage Calibration
|
Hi,
I`m trying to calibrate my DRS4 evoluation board to an input range of 0-1V but it doesn`t work.
1) First I tried to calibrate it with the drsosc (version 5.0.3) Software. The -0.5V - 0.5V calibration works, but during the 0 - 1V calibration |
Wed Jun 13 13:23:17 2018, Julian Kemp, Maximum analog input voltage
|
Dear all,
I have been wondering what the maximum analog input voltage for the DRS4 V5 evaluation board is. It came with a sticker indicating that it is
"2.5V pk Max". On the other hand, when checking the manual (https://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf), it says maximum allowed |
Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage
|
Thank you! That solves my problem.
Stefan
Ritt wrote:
In principle the numbers in the manual are correct. But they relate |
Fri Oct 13 03:39:01 2017, Jonathan Wapman, Raspberry Pi Connection Failure
|
I am currently attempting to use a raspberry pi to connect to the DRS 4 board. I whenever I try to use the DRS Command Line TOol, Revision 21435 to connect
to the drs board, I get the error
"musb_open: libusb_open() error -3" |
Wed Oct 25 19:44:25 2023, John Westmoreland, WaveDREAM Design
|
Hello All,
Are there any design resources available for the WaveDREAM PCBA's?
Thanks In Advance, |
Wed Oct 25 19:52:33 2023, John Westmoreland, WaveDREAM Design
|
Stefan,
Oh, didn't realize that.
Thanks! |
Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0?
|
In the equations for computing the corrected time for channels other than channel 1, does anyone know what the term t0,0 refers
to? This is the last term in the last equation on page 24 of DRS4 Evaluation Board User’s Manual, Board Revision 5 as of January 2014, Last
revised: April 27, 2016. |
Fri Oct 16 09:51:03 2009, Jinhong Wang, DSR4 Full Readout Mode
|
Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after
38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for |
Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4
|
Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor
Qi An, who is my PhD supervisor. |
Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4
|
Hello Mr. Stifan.Ritt
In the DSR4 datasheet, it is mentioned
that there is an additional buffer at each analog output, this buffer shifts the the differential range of -0.5V~0.5V to 0.8V~1.8V. Does it mean that this
buffer shifts a voltage of about 1.3V for the primary differential range?
Again for the differential |
Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4
|
|
Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4
|
Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation
of trigger signal to stop DRS4 sampling process for readout of sampled waveform. |
Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4
|
Stefan Ritt wrote:
|
Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4
|
Stefan Ritt wrote:
|
Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model
|
Stefan Ritt wrote:
|
Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4
|
Stefan Ritt wrote:
|
Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4
|
Stefan Ritt wrote:
|
Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4
|
Hi Stefan,
I found DRS draw a lot of current when applied Reset after power on, and the PLL does not work properly. I believe
there was something that I misunderstood. So, what will happen when Reset is applied more than once after power on? . Though the chip worked well |
Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4
|
Stefan Ritt wrote:
|
Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4
|
Stefan Ritt wrote:
|
Mon Jul 19 12:07:04 2010, Jinhong Wang, Fixed Patter Timing Jitter
|
Hi Stefan, can you give some suggestions on determination of fixed pattern timing jitter of DRS4? Thanks~ |
Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS
|
Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS)
= 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained
from DC offset Correction, hence 11.5 bit is for DC input, am i right? If true, what about ENOB for AC input in the whole analog bandwidth? thanks~ |
Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer
|
Stefan Ritt wrote:
The design of high frequency differential input stages with the DRS4 is a challenge, since the chip |
Mon Jul 4 05:06:00 2011, Jinhong Wang, Fixed Patter Timing Jitter
|
Stefan Ritt wrote:
|
Tue Jul 12 09:49:08 2011, Jinhong Wang, Fixed Patter Timing Jitter
|
Stefan Ritt wrote:
|
Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors
|
Hi Stefan,
A quick question, what is the typical variation of the sampling capacitors in DRS4? Will this variation be significant to affect your sampling
result? |
Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors
|
Stefan Ritt wrote:
|
Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors
|
Jinhong Wang wrote:
|
Tue Jul 19 02:35:04 2022, Jingyu Zhang, Increase event rate, use ROI mode, and install sw from source in Mac
|
Dear experts,
We are trying to increase the event rate of the DRS4. We looked into the ROI
but couldn’t figure out how to run in ROI mode. We are wondering if there is pre-existing firmware for this? We also tried to download and build |
Tue Mar 28 21:53:12 2017, Jim Freeman, drscl doesn't find eval board but drsosc does (Windows 7)
|
I cannot find the EVAL board using drscl version 5.06 while the drsosc works fine. I tried 2 different eval boards and 2 different computers and the
same effect. I looked under device manager at the libusb and the drs4 was there, and checked the driver which was found to be up to date. |
Tue Mar 26 01:17:59 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
All I'm trying to do is cascade one input signal, though all available channels, so that I end up with 8*1024 bins per event.
Here is the read out on my board/chip: |
Fri Apr 5 02:21:33 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Stefan Ritt wrote:
|
Wed Apr 10 22:41:21 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Stefan Ritt wrote:
|
Thu Apr 11 23:32:57 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Stefan Ritt wrote:
|
Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
|
Hi Steffan,
I have a question about how to acquire the stop channel:
Process: Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, |
Fri Nov 5 01:10:25 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
|
Jiaolong
wrote:
Hi Steffan, |
Fri Nov 5 01:12:10 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
|
Thanks for your advice. The problem has been solved by setting the srin again while reading out from srout.
Stefan
Ritt wrote:
The problem must be on your side, since the Write Shift Register readout |
Mon Oct 25 18:48:04 2021, Javier Caravaca, Trigger multiple boards independently
|
Hello,
I recently acquired 4 DRS4 boards and I wanted to ask if it was possible to trigger them independently from the same computer.
I know that you can daisy-chain boards and trigger them all at the same time, but in my case, each of my boards record independent events, so |
Tue Oct 26 23:18:32 2021, Javier Caravaca, Trigger multiple boards independently
|
Thank you Stefan. Actually I noticed that the source code of drs_exam was available after I started this thread, and that was the solution that
occurred to me too. I'll give that a try.
A related question is: if the 4 boards are triggering at max rate (500Hz), would the total data throughtput (of the four boards together) be |
Fri Jun 9 04:11:40 2023, Javier Caravaca, Different sampling rates in multi-board configuration
|
Hello,
Is it possible to have different sampling rates in multi-board configuration? I tried using the scope application but I am unable to change
the sampling rate independently. |
Tue Nov 16 01:27:51 2021, Jacquelynne Vaughan, V3 board, only one channel works, all components at each channel input working
|
Hi everyone,
I'm still looking through the forum for an answer to this question, but thought I'd go ahead and post anyway just in case it hasn't
been answered yet. If it has I can take this post down. |
Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting
|
Hello,
I have designed four DRS4 chips (36 channels) on my board running at 1GHz (REFCLK=488.28KHz) and ROI mode. All 4 chips' REFCLK, DWRITE, RSRLOAD,
and SRCLK are buffer driven by the same source. SRCLK is set to 40MHz to reduce the readout time. |
Tue Jan 12 17:57:03 2016, Jack Bargemann, Compiling DRS-exam
|
I am trying to compile drs-exam, but am getting an error message I do not understand:
1>musbstd.obj : error LNK2019: unresolved external symbol _usb_open referenced in function _musb_open
1>musbstd.obj : error LNK2019: unresolved external symbol _usb_close referenced in function _musb_close |
Wed Jun 20 10:40:21 2012, Ivan Petrov, triger for measuring time between pulses in channels
|
Stefan Ritt wrote:
|
Wed Jun 20 14:36:01 2012, Ivan Petrov, triger for measuring time between pulses in channels
|
Stefan Ritt wrote:
|
Mon Jul 9 14:14:48 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows
|
Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++
with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions
will be helpful. Thank you. |
Wed Jul 11 10:04:51 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows
|
Stefan Ritt wrote:
|
Thu Jul 18 01:03:44 2019, Ismael Garcia, Trace Impedance
|
Hi Steffan,
I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on |
Fri Jul 19 01:37:09 2019, Ismael Garcia, Trace Impedance
|
When you're refering to laying a 50 Ohm trace, you're referring to the SMA input and not the interface between the output of the Op-AMP(THS4508)
buffer
and the inputs of the DRS4(IN0-IN8). Is there a recommended diffential impedance for IN0-IN8? |
Tue May 19 14:14:45 2015, Ilja Bekman, DRS4 firmware UCF constraints
|
Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
|
Wed Oct 7 13:06:34 2015, Ilja Bekman, Voltage Calibration with signal on the input
|
|
Sun May 2 18:36:14 2010, Ignacio Diιguez Estremera, DRS4 chip model
|
Hi all,
i'm an electronics engineering student at UCM (Madrid) working on my master's thesis within the CTA collaboration. I'm designing the readout electronics
for the telescope's camera, and i'm focusing in using GAPDs instead of PMTs and using the domino chip for the sampling of the signal. I was wondering if |
Mon May 3 17:06:02 2010, Ignacio Diιguez Estremera, DRS4 chip model
|
Stefan Ritt wrote:
|
Mon May 3 23:21:55 2010, Ignacio Diιguez Estremera, DRS4 chip model
|
Stefan Ritt wrote:
|
Tue May 4 16:23:16 2010, Ignacio Diιguez Estremera, DRS4 chip model
|
Stefan Ritt wrote:
|
Wed May 5 22:30:50 2010, Ignacio Diιguez Estremera, Random noise spec in datasheet
|
Hi,
According to DRS4's datasheet, the random noise is 0.35mVrms. Is this the input equivalent noise voltage? It is computed over the 0-950MHz frequency
band? |
Fri Nov 3 12:11:14 2017, Hεkan Wennlφf, Triggering using AND
|
Hi!
I'm using the DRSOsc program, and I have a question that I need a bit clarified;
When triggering using AND between two channels, am I then triggering on rising/falling edge of both channels, or on the actual values? |
Tue May 1 02:00:40 2018, Hyunseong Kim, DRS4 using drs_exam.cpp to save as binary files
|
Hi,
I would like to save the waveform in a .dat binary file using drs_exam.cpp.
I know the distributed software allows us to save as binary files with the save button, but I currently need to save multiple runs using |
Fri Jul 5 12:46:45 2013, Hermann-Josef Mathes, Missing methods in drs-4.0.1.tar.gz
|
Hi,
while trying to create python bindings for the DRS stuff using SWIG 2.0.4, two undefined methods prevent the python interpreter from loading the
generated shared library. These methods are: |
Wed Aug 7 15:05:59 2013, Hermann-Josef Mathes, Repeated time calibration
|
Hi,
is there any (obvious) reason why it is not possible (or not indended) to repeat the time calibration of a DRS4 eval board several times. I get |
Wed Aug 7 15:20:33 2013, Hermann-Josef Mathes, Repeated time calibration
|
Stefan Ritt wrote:
|
Wed Mar 5 21:54:13 2014, Hermann-Josef Mathes, Software drs-5.0.0 fails to compile (drsosc)
|
Hi,
the latest software drs-5.0.0.tar.gz fails to compile on my freshly installed SuSE 13.1 whereas the previous 4.0.1 is compiling out-of-the-box.
|
Mon Mar 16 16:07:39 2015, Hermann-Josef Mathes, Running 2 instances of a DRS DAQ program
|
Hi,
we want to run two instances of our little DRS DAQ program but obviously the first instance started always claims all DRS boards for itself and
the other one exits with an error. The 2 boards used in the example below have the serial number # 2413 and #2414 and are v5 boards. |
Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279?
|
Hi, Stefan,
I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware
13191.
Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.
Thanks,
Heejong
|
Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board
|
Stefan Ritt wrote:
Several people asked for s simple application to guide them in writing their own application to read out |
Thu Jan 19 23:26:26 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4
|
Hello,
I'm using DRS4 evaluation board version4 in Linux (Scientific Linux 5).
Version4 software (drs-4.0.0) was installed without any troubles. |
Fri Jan 20 23:50:39 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4
|
Stefan Ritt wrote:
|
Sun Jan 31 23:52:15 2010, Hao Huan, Failure In Flashing Xilinx PROM
|
Hi Stefan,
I have an old-version DRS4 evaluation board which doesn't have the latest firmware. I tried to flash the drs_eval1.ipf boundary
scan chain into the XCF02S PROM with Xilinx IMPACT, and the firmware seemed to go through into the PROM. However, when I started the DRS command line interface |
Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
|
Hi Stefan,
in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However |
Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
|
Stefan Ritt wrote:
|
Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
|
Stefan Ritt wrote:
|
Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
|
Stefan Ritt wrote:
|
Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit
|
Hi Stefan,
I read in the datasheet that every time after power up the Domino wave in DRS4 needs to be started and stopped once to initialize
the Domino circuit. However in your firmware it seems the chip immediately goes into the idle state after reset. Is that Domino circuit initialization |
Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data
|
Hi Stefan,
thanks to your help I can now successfully keep the Domino wave running at a stable frequency and maintain the channel cascading
information in the Write Shift Register. (Since you told me WSR always reads and writes at the same time, I think I need to rewrite the information back |
Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data
|
Hao Huan wrote:
Hi Stefan, |
Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
|
Hi Stefan,
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is
toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz? |
Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip
|
Hi Stefan,
I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth in the transparent
mode is 50MHz. Since in the transparent mode the input is routed to the output, does it mean the input bandwidth also gets reduced in the transparent mode? |
Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
|
Stefan Ritt wrote:
|
Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration
|
Hi Stefan,
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. If I want to run the Domino
wave nominally at 1GHz, i.e. with a reference clock frequency around 0.5MHz, is there any recommended loop filter configuration? Is the setup of the evaluation |
Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration
|
Hi Stefan,
according to the DRS4 datasheet, if we want an input range centered around U0, the ROFS should be 1.55V-U0. However when I read
the codes of the evaluation board application, ROFS seems to be 1.6V-1.25*U0 where the coefficient 1.25 is said to come from sampling cell charge injection |
Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data
|
Hi Stefan,
when I sample a constant input with the DRS 4 chip, there was a baseline variation showing up as a saw-tooth pattern which grows
with the absolute value of the differential input. Do you think this is the kind of baseline variation mentioned in the evaluation board manual, i.e. coming |
Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4
|
Hi Stefan,
on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our
board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization |
Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4
|
Stefan Ritt wrote:
|
Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4
|
Stefan Ritt wrote:
|
Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS
|
Hi Stefan,
I read in the DRS datasheet that the bandwidth for the transparent mode OUT+ is only 200MHz which I think cannot be improved
by any active input buffer; so if you want to operate the chip for really high frequency input, would it be better to feed on-board discriminators not |
Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout
|
Dear Dr. Ritt,
In the DRS 4 datasheet it is recommended to sample the analog output of the chip after 8~10 ns of the SRCLK edge for it to stablize
and thus a phase shift between SRCLK and the ADC sampling clock is necessary. However in the latest version of the evaluation board firmware the phase-shifted |
Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller
|
Hi Stefan,
I have a question regarding the DRS 4 evaluation board firmware for the 8051 controller embedded in the CY7C68013 USB chip:
on the board the controller is running at 12 MHz and the FIFO interface of the USB chip is running at 30 MHz, so the number of delay cycles for synchronization |
Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s)
|
Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. |
Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points
|
Dear All,
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g.
a sampling point all 200ps for 5GS/s). |
Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points
|
Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best, |
Sat Aug 29 22:00:30 2020, Hans Steiger, Dynamic Range Evaluation Board and Software
|
Dear Evaluation Board Team,
currently I am facing the problem of digitizing pulses with an amplitude of -0.6V to -0.8V. As the dynamic range of the board is 1Vpp, this should |
Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading
|
Dear All,
I have a board with Channel Cascading Option. I have the problem, that it seems to be impossible to run all 4 Channels simultaneously for digitizing
pulses. I can just run even or odd channels but not even and odd ones? If I run in combined option, My question: If a board comes with this combined option, |
Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail
|
Hi,
has anyone experienced a shutdown of the DRSosc.exe or DRScl.exe when executing a Timing Calibration? Also, when we add the command b->CalibrateTiming(NULL);
to the drs_exam.cpp and run the exe, our program shuts down immediately and windows shows an error message (identical to DRSosc and DRScl). |
Wed Sep 7 17:28:25 2011, Hannes Friederich, DRS4 and AD9222
|
Guillaume Blanchard wrote:
Normal
0
21
|
Wed Nov 21 08:34:52 2012, Gyuhee Kim, Question for using Multi board
|
Hi.
I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ. |
Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board
|
Stefan Ritt wrote:
|
Mon Dec 3 08:32:28 2012, Gyuhee Kim, Another question about using multi boards.
|
Hi.
I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!) |
Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards.
|
Stefan Ritt wrote:
|
Wed Sep 7 16:45:17 2011, Guillaume Blanchard, DRS4 and AD9222
|
Normal
0
21
false
false
false
MicrosoftInternetExplorer4
|
Fri Sep 9 09:28:57 2011, Guillaume Blanchard, DRS4 and AD9222
|
Thank you for your answers,
Another question : Have you ever tried to split the differential signal at the output of the DRS4 chip ? For
example to feed both an AD9222 and a diff. amplifier (followed by discriminators) ? |
Mon Apr 23 10:38:51 2012, Guillaume Blanchard, DRS4 Initialization
|
Hello,
I am writing a VHDL code to drive a DRS4 chip.
In order to configure the DRS4 chip, I have to set the "Config Register" and the "Write Shift Register" then ... (I do not |
Thu Jun 18 17:33:05 2015, Gregor Kramberger, drs 5.03 and windows 8.1
|
I have problems with driver installation on windows 8.1 (software version 5.03). I have sen that that has been an issue before (driver signing)
and I would like to know if this has been solved. We run several DRS4 evaluation boards on different PCs all running Win7 without any problems.
Therefore we are almost confident that it is related to Win 8.1. Thanks. |
Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1
|
Gregor Kramberger wrote:
I have problems with driver |
Fri Jan 13 12:58:22 2017, Gregor Kramberger, DRS software doesn't work under Windows XP SP3
|
Hi all
I have a problem with running the DRSOSC under windows XP SP3. We have some hardware which is not supported under newer versions of windows and
we would like to use DRS boards along it, therefore we would higly appreciated any help in that direction. We have installed the software (V 5.03) to two |
Mon Apr 10 08:50:11 2017, Giovanni Bruni, drs4 registers behaviour
|
Hej everyone!
I have some questions regarding what happens to some DRS registers in some scenarios:
1. How are the registers affected by a RESET? According to the data sheet all the CONFIG REGISTER bits are initilialized to 1. But what about the |
Mon Apr 10 13:41:41 2017, Giovanni Bruni, drs4 registers behaviour
|
Hej Stefan! Thank you for your answer!
Just to be sure to have understood properly:
1. Using the RESET line should be avoided. And in any case, the CONFIG register and the WRITE SHIFT register need to be initialized "by hand" |
Tue Apr 11 09:07:33 2017, Giovanni Bruni, drs4 registers behaviour
|
Thank you Stefan for replying!
I have still the RESET issue in mind: how would you suggest to reset properly the DRS? Is there a particular procedure to follow instead of just
sending a negative pulse to the RESET pin? Is it preferable to turn the DRS off and then restart? |
Fri Nov 18 16:38:42 2016, Gerard Montarou, LabView
|
Hello,
Did you start to write some VI to interface DRS4board with labview ?
i also have in mind to do that.I am surprised that nobody alraedy did it since there is no answer toyour question |
Sun Sep 23 02:22:46 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
|
Hello Stefan,
I am using the DRS4 board connected to a Raspberry PI and through the drsosc application. I am interested on using the "Trigger OUT"
signal to do some extra data processing with NIM modules. According to the manual, for each hardware trigger a TTL pulse of 150 ns width should be send |
Wed Sep 26 18:25:07 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
|
Thank you very much for the answer, I really appreciate your help.
Thanks!
Gerard |
Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
|
Thank you very much for the answer, I really appreciate your help.
Thanks!
Gerard |
Wed Feb 27 13:47:32 2013, Georg Winner, Chip Test - Cell Error
|
When starting Chip Test in DRS Command Line Interface, I receive the following message:
Cell error on channel 1, cell 5: -154.4 mV instead 0 mV
|
Mon Mar 25 11:12:53 2013, Georg Winner, Differences in Source Code
|
I have noticed some differences in the source code between Windows (4.0.0) and Linux (4.0.1) Version.
drs_exam.cpp: In the windows version when setting the trigger there is no part "if (b->GetBoardType() == 8) {...} else {...}" like
in Linux version. So under Windows drs_exam does not start readout of DRS 4 Evalutation Board V4, because it does not get the trigger, under linux the |
Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource
|
Hi
I have a question about the function SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp)
In the implementation there is the following comment: |
Sat May 23 11:03:20 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz
|
Hi
We are working with the DRS 4 V5 version and we investigated an issue with the trigger at rates below ~120 Hz.
As long as we have a trigger rate of more than 125 Hz. everything seems to work fine and we are recording more or less all events. |
Tue May 26 11:27:27 2015, Felix Bachmair, DRS4 firmware UCF constraints
|
> > Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
> >
> > I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
|
Fri Jun 5 13:15:35 2015, Felix Bachmair, DRS4 firmware UCF constraints
|
Hi Stefan,
No we only use one evaluation board. We use the evaluation board as a part of our beam test setup. It includes a telescope based on the current PSI46V2.1
CMS Pixel chip and a trigger logic board for triggering the telescope and the evaluation board. This includes a
|
Thu Jul 2 08:53:17 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz
|
Hi,
We did a further investigation of this problem:
We figured out that this issue seems to be related to the kernel. |
Thu Jul 2 13:20:51 2015, Felix Bachmair, Creation of Object files
|
HI,
We are using the DRS4 Board in the EUDAQ framework [1]. We wrote a a Producer based on the software of the evaluation board, which is using the
DRS class/header/src files. |
Mon Jul 6 11:30:56 2015, Felix Bachmair, Creation of Object files
|
Hi Stefan,
That's fine for me. I thought it might be interesting for others as well..
Cheers |
Tue Jul 7 09:29:21 2015, Felix Bachmair, Creation of Object files
|
Yes of course no problem.
You can download via github https://github.com/veloxid/DRS4-v5-shared and I
also put it in the attachment. |
Fri Aug 7 20:32:15 2015, Felix Bachmair, DRS4
|
Hi
Did you copy the udev rule 41-drs.rules into /etc/udev/rules.d/ ?
Which operating system are you using? |
Sat Apr 2 11:21:10 2016, Felix Bachmair, Question about timimng calibration
|
Hi,
I am trying to understand some details about the timing calibration.
We wrote our own code but we more or less use the ideas of the Oscilloscope class. |
Thu Dec 13 12:03:29 2012, Evgeni, DRS-4 trigger
|
How to configure DRS oscilloscope for the oscillations with an amplitude greater than the value of the exposed
in the trigger (internal). |
Thu Dec 13 19:49:47 2012, Evgeni, DRS-4 trigger
|
Stefan Ritt wrote:
|
Fri Dec 14 10:07:14 2012, Evgeni, DRS-4 trigger
|
Evgeni wrote:
|
Fri Dec 14 10:07:54 2012, Evgeni, DRS-4 trigger
|
Stefan Ritt wrote:
|
Mon May 22 18:27:56 2017, Esperienza Giove, Invalid magic number 0000
|
Hello everybody!
After some times i init my board, or if i stop the program during the acquisition, i get the error message "Invalid magic 0000". The
only way i can solve this problem is to physically disconnect and plug in again the USB cable. |
Thu May 25 20:17:41 2017, Esperienza Giove, Invalid magic number 0000
|
Hello, thanks for your answer. Unluckily if i try to reset in this way it keeps hanging
musb_write: requested 10, wrote 0, errno -7 (Unknown error 18446744073709551609)
musb_read error 0 |
Thu May 25 20:20:57 2017, Esperienza Giove, Invalid magic number 0000
|
Hello, thanks for your answer. Unluckily if i try to reset in this way it keeps hanging
musb_write: requested 10, wrote 0, errno -7 (Unknown error 18446744073709551609)
musb_read error 0 |
Tue May 30 20:45:30 2017, Esperienza Giove, Setting input range
|
Hello,
is it possible to set a completely negative input range like -1 to 0 or -0.95 to 0.05 ? |
Tue May 30 21:22:10 2017, Esperienza Giove, Setting input range
|
Thank you
Stefan
Ritt wrote:
See elog:531 |
Thu Jul 6 15:10:48 2017, Esperienza Giove, Trigger setting (AND AND) OR (AND AND)
|
Hello there,
is it possible to setup trigger in double AND configuration (a pair in and or other pair in and).
eg (CH 1 AND CH 2 ) OR ( CH 3 AND CH4) |
Tue May 21 12:39:00 2013, Enrico Conti, mac osx 10.6
|
Hi,
I would like to use the DRS4 with my macbook pro running osx 10.6.8.
|
Tue May 21 17:45:05 2013, Enrico Conti, mac osx 10.6
|
>
> Can it be that you have a old PowerPC MAC? I have no experience with that, but probably you have to adjust the Makefile
> ans set some flags correctly for PPC instead of Intel.
|
Tue May 21 17:48:45 2013, Enrico Conti, mac osx 10.6
|
>
> it looks like 64bit vs 32bit problem, you have to compile all libraries for the same architecture. Maybe, make clean to
> remove all precompiled object files .o and recompile it again. Try to compile first that simple example without wxWidgets.
|
Tue May 21 18:30:11 2013, Enrico Conti, mac osx 10.6
|
> > >
> > > it looks like 64bit vs 32bit problem, you have to compile all libraries for the same architecture. Maybe, make clean to
> > > remove all precompiled object files .o and recompile it again. Try to compile first that simple example without wxWidgets.
|
Fri May 24 17:58:07 2013, Enrico Conti, mac osx 10.6
|
> > >
> > > it looks like 64bit vs 32bit problem, you have to compile all libraries for the same architecture. Maybe, make clean to
> > > remove all precompiled object files .o and recompile it again. Try to compile first that simple example without wxWidgets.
|
Sat May 25 12:45:46 2013, Enrico Conti, mac osx 10.6
|
> > I made some progress. Understood what was wrong in the make phase. You have only to add the option -arch i386 in the CFLAGS line of the makefile.
> > Then the make is ok, it produces the 3 executables. drs_exam and drscl seem to work correctly.
> > DRSOsc.app does not work as app, in the sense that if you click it, an error message comes saying "You can't use this version of the application DRSOsc.app |
Tue Sep 22 17:45:26 2020, Elmer Grundeman, External triggering
|
Dear all,
I had a question about timing jitter and external triggering.
I trigger the board externally with a 3V pulse from a DG645 delay generator and as a test I use the gated charge function to integrate another |
Wed Oct 7 11:17:52 2020, Elmer Grundeman, External triggering
|
I will try that, thanks!
Stefan
Ritt wrote:
The trigger is there only to trigger the chip, but cannot be used as |
Tue May 27 13:46:18 2014, Dominik Neise, Spikes in DRS4 data on custom baord.
|
We see quite some spikes in our DRS4 sampled data in FACT. We see different types of spikes:
single cell spikes, usually showing a large amplitude of 200mV
double cell spikes, usually only in the order of 20mV.
Even triple and quadro cell spikes are rarely seen.
The double cell spikes often occur as symmetrical double cell spikes mirrored |
Fri Mar 11 19:50:18 2016, Dominik Neise,
|
Hello Stefan,
I just stumbled again over a phrase in the DRS4 datasheet I never really understood, but didn't find the time to ask.
On page 8 it says: "An internal circuit ensures that the write signal is always 16 cells wide." |
Wed Jun 1 22:29:01 2016, Dominik Neise, problems when stop cell >= 767 ??
|
Hello Stefan,
some colleages told me a story, I was neither able to confirm nor find anything in the datsheet about. According to them:
For some internal reason of the DRS4, if the “stop capacitor” of the DRS4 is >= 767, the true stop channel is one |
Mon Feb 29 12:58:17 2016, Dmitry Philippov, baseline shift
|
Hello! My name is Dmitry. I am from SiPM Lab is NRNU MEPhI (Russia, Moscow). We bought DRS4 evaluation board V5 with firmware 21305. We use 5.0.4 build
21911 2015-11-23 software version (and before that we used 5.0.3 build 21508, 2014-10-15) with Windows 7 32bit.
We observe some strange behaviour. When we save waveforms (in xml or binary data) we see that some of them have the baseline shifted of about |
Thu Feb 28 10:47:14 2013, Dmitry Hits, clock and trigger outs
|
Hi,
I am considering using the DRS4 evaluation board as an ADC card for the wire chamber in the physics lab (VP) experiment at ETH. However, the wire
chamber has 8 outputs, so I would need to have two of such boards. Is it possible to synchronise them, online or offline? From the website, it looks
|
Mon Apr 8 18:11:02 2013, Dmitry Hits, binary to root
|
Hi,
Does anyone has a program that converts a binary file from drsosc output to a ROOT tree format? |
Tue Jul 9 11:40:00 2013, Dmitry Hits, cannot save in binary format
|
Hi,
I would like to save the waveform in a binary format. When I click Save then change format from xml to dat in the menu. I still get xml format
but with dat extension. |
Tue Jul 9 14:00:49 2013, Dmitry Hits, cannot save in binary format
|
Stefan Ritt wrote:
|
Wed Nov 6 11:53:28 2013, Dmitry Hits, flickering screen for drsosc
|
Hi,
I have install drs software on ASUS EeeBox with Ubuntu 12.04 LTS. When I try to use ./drsosc the oscilloscope window flickers. Can you suggest |
Mon Nov 18 11:20:15 2013, Dmitry Hits, flickering screen for drsosc
|
Stefan Ritt wrote:
|
Mon Nov 18 15:49:01 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis
|
Dear Stefan,
I am trying to synchronise the readout of two test boards, one is the DRS4 test board, the other is PSI46 test board (used for the readout of CMS
pixel chip) for the offline analysis. I think that the most secure way to accomplish this is to pass a trigger number from one test board to the other. |
Tue Nov 26 15:36:39 2013, Dmitry Hits, reducing sampling speed
|
Dear Stefan
Is there an easy way to reduce sampling speed below 0.7 GSPS? I would like to record traces up to 5 usec long.
Thank you |
Fri Dec 13 10:37:18 2013, Dmitry Hits, input protection in DRS4 evaluation board
|
Dear Stefan
Last month I was using a DRS4 evaluation board to digitise the signal from the charged particles in piM1 beam line at PSI. The beam in piM1 is
a mixture of pions with a small percentage of protons. Pions are close to minimum ionising and were producing the signals on the order of 250 mV (Landau |
Mon Dec 16 11:09:25 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis
|
Stefan Ritt wrote:
|
Fri Sep 12 11:52:21 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer
|
Hi everyone,
Has anyone tried to synchronize 2 (two) DRS4 evaluation boards readout by the same computer? I have read about some attempts on this board in the
past, but I do not know if they have succeeded. If yes, could you share your experience and/or software. |
Fri Sep 12 13:37:42 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer
|
Stefan Ritt wrote:
|
Fri Sep 12 14:57:22 2014, Dmitry Hits, compilation error for v5.0.2
|
Hi,
I am getting the following compilation error when trying to compile version 5.0.2 software:
src/DOFrame.cpp:617:14: error: invalid conversion from ‘char*’ to ‘wxChar {aka wchar_t}’ [-fpermissive]
I |
Fri Sep 12 16:38:24 2014, Dmitry Hits, compilation error for v5.0.2
|
Stefan Ritt wrote:
|
Mon Feb 29 13:33:06 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
|
Dear Stefan,
I daisy-chained two boards (master sn#: 2514 - slave sn#: 2513) each with 2048 samples. However, when I use drsosc and put check mark in "configure
multi-board daisy-chain" I see only 1024 samples. Namely, the first 1024 samples, the last part is missing. When I remove this check mark, I |
Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
|
Hi Stefan
Any chance you have time to fix the software for multiboard configuration with 2048 samples each. I tried 5.0.5, but drsosc still shows
only half of the waveform. |
Wed Feb 16 14:06:45 2022, Dmitry Hits, Sliders missing in drsosc
|
Hi everyone,
Did anyone have a "missing sliders problem" in GUI (see attachment) accompanied by the following message in the terminal.
(drsosc:4611): Gtk-WARNING **: 14:05:11.249: Negative content width -4 (allocation 20, extents 12x12) while allocating gadget (node scale, owner |
Thu Nov 16 02:55:44 2017, Diego Yankelevich, Averaging capabilities
|
The Display window in the Oscilloscope software shows averaging capabilites but I have not been able to activate these. Is it possible to activate averaging
with the existing oscilloscope software? Thanks |
Tue Dec 12 00:25:50 2017, Diego Yankelevich, External trigger using Raspberry Pi
|
Dear Steffan:
We have been able to use the DRS4 using a Raspberry Pi but we have not been able to use the external trigger. What we are doing is basically
comment out the code shown below (downloaded from PSI) to use the hardware trigger and uncomment the code to use the external trigger. We have not been |
Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit
|
Dear Stefan,
I have emailed drs4@psi.ch a couple of times regarding the pricing of the evaluation kits for academic use in India and have not received any
reply and hence writing in this forum. Could you please help me in this? |
Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue
|
Hi,
We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
|
Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue
|
Thanks a lot for the quick response.
We will do as you suggest.
|
Mon Oct 14 09:32:33 2019, Danyang, how to acquire the stop position with channel cascading
|
Hi Steffan,
In DSR4 DATASHEET Rev.0.9 Page13, there is a paragraph "If the DRS4 is configured for channel cascading
or daisy chaining, it is necessary to know which the current channel is where the sampling has been stopped. This can be |
Mon Oct 14 11:45:06 2019, Danyang, how to acquire the stop position with channel cascading
|
I tried the logic in my designed board. The results are shown in the picture: Srout keeps low when A3-A0 is
set to 1101 and srclk is set as you mentioned. And the drs4 chip does not output sine wave in such configuration.
Srout signal only reacts after the rsrload signal is pulled high and A3-A0 is not 1101. |
Mon Oct 14 13:44:26 2019, Danyang, how to acquire the stop position with channel cascading
|
Yes, firstly I configured the chip with 4x2048 bins by setting the Write Shift Register to 01010101b, A3-A0 keeps 1101----> secondly
I enabled the domino wave, wait some time for stable, A3-A0 keeps 1111 ---->thirdly stops the domino wave when the trigger comes,
A3-A0 keeps 1101 (or 1010, 0000)----> forthly send the clock pulse to the srclk pin, A3-A0 keeps 1101, srout |
Tue Oct 15 08:14:17 2019, Danyang, how to acquire the stop position with channel cascading
|
Thanks a lot. The problem is solved when A3-A0 is set 1101 and srclk keeps low.
Best Regards,
Danyang |
Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
(Board Type:9, DRS4)
Hello,
I´m trying to reach the timig resolution of about 2.5ps as written in the manual. |
Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Hello Stefan,
Chn2 & Chn3 were used for delay-determination as you can see on the second picture.
|
Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Hello Stefan,
thanks for the paper. That makes sense. I thought about sth. like that but wasn`t sure. Couldn´t check higher frequencies (limit of my
function generator). |
Sat Jan 28 14:11:58 2017, Danny Petschke, AND trigger problems
|
Dear Stefan,
I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals
are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude |
Thu Mar 19 07:37:52 2015, Daniel Stricker-Shaver, Running 2 instances of a DRS DAQ program
|
I don't know if it helps, but we measured the time resolution between two independendly running v3 boards using a single PC (latest software) in
Linux. (http://arxiv.org/abs/1405.4975)
You start the DRS DAQ program with only one USB board connected, first. Afterwards connect the second board and start another session. If you |
Tue Apr 21 13:03:38 2015, Daniel Stricker-Shaver, DRS4 Evaluation Board Baseline/Voltage Calibration
|
I also use Ubuntu 14.04 LTS and for my V3 borad I have to use drsosc 4.x or ealier to perform the calibration.
Stefan
Ritt wrote:
1) I tried to cablirate a V5 board with drsosc 5.0.3 and it just worked |
Sat Apr 23 12:33:17 2016, Daniel Stricker-Shaver, Negative fCellDT values from GetTimeCalibration()
|
Hi Kyle,
If I remember right the negative sampling width happens only for 498 and at high sampling speeds. It is described in a paper from Stefan:
http://arxiv.org/pdf/1405.4975.pdf |
Mon Mar 21 10:38:27 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run
|
Dear Stefan Ritt,
I am using a DRS4 v5 to do timing measurements of Positron lifetime. I use the DRS Oscilloscope with triggering on 2 channels when I have
a coincidence. Attached is a picture with all the setting that I use. When I use the DRS4 for a long measurements of 5 million events for a couple of hours, |
Mon Apr 4 11:41:26 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run
|
Dear Stefan Ritt,
Yes I use Windows 7, If the DRS Oscilloscope program stays on for a couple of hours without saving the
data, the problem will occur. It seems it happens more often when there is data writing and when the rate of events is slow, about 100 events per second, |
Wed Apr 6 09:43:52 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run
|
At hight rates I worked with files of up to 20 GB so I don't think this is the problem.
I will try to run it under Ubuntu and see if i can recreate the problem.
Thank you very much for the quick responses and help. |
Wed Apr 6 09:46:10 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run
|
Martin Petriska
wrote:
Stefan |
Wed May 13 00:52:51 2015, Cosmin Deaconu, Getting Trigger Source
|
I'd like to be able to know which channel (0,1,2,3 or external) was responsible for the trigger. DRSBoard::GetTriggerSource() seems to always
return 1. Is there a way to get this information? Using the DRS4 evaluation board and software version 5.0.3.
Thanks, |
Wed May 13 01:07:36 2015, Cosmin Deaconu, DRS4 Evaluation Board + Powered USB Hub
|
I am trying to use 4 evaluation boards with a powered USB hub (since eventually, I will have to do this on a laptop). It seems like destroying
the DRS object is insufficent to properly close the boards when on the hub (i.e. I get usb read errors next time I run my program). When all the boards
are plugged into the computer, all is fine. This is on Linux using libusb1. My guess is something about resetting the port doesn't work properly |
Fri Nov 4 17:41:03 2016, Christian Farina, Missing Header
|
Hello everybody,
I am completely new to this, so please bear with me.
I am trying to install the applications on my laptop. I downloaded and untar-ed the drivers and applications for Linux as described in the evaluation |
Wed Nov 9 17:19:48 2016, Christian Farina, Missing Header
|
Thank you Stefan, that was just what I needed.
Also, I have another question, if I am allowed to ask on this forum. I am trying to study how the time calibration of the DRS is done. Can you
point me to the script in which this is done? |
Thu Nov 10 20:54:45 2016, Christian Farina, Missing Header
|
Hi Stefan,
I have already read the paper. I was just unsure where the calibration code was located. Thank you so much for all your help.
Christian |
Thu Apr 13 16:42:21 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
|
Hello everybody,
I was trying to create a stand-alone program that would perform a time calibration on the board. My goal would be the following.
- acquire about 10k sinus waveforms |
Thu Apr 13 16:54:32 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
|
Hi Stefan,
Thank you for your reply. I have read the paper already. I looked through the code and I understand that the LTC and GTC are performed by the
AnalyzeSlope and AnalyzePeriod functions, respectively, correct? It seems to me to be a complicated business to re-write that part from scratch, at least |
Thu Apr 13 17:10:58 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
|
Thank you for your help Stefan. I will try to get the TC part isolated.
Stefan
Ritt wrote:
Than you can try to isolate the code. Note that different SCAs might |
Wed Mar 9 09:57:20 2016, Christian D, LabView
|
Hi,
I would like to use the DRS4 board with LabView for fast readout.
Do you know anyone who has written a VI for that? |
Sun Oct 19 14:36:54 2014, Chris Tully, coverting the xml file format into binary
|
Hi,
Is there a straightforward way to convert the xml file format into the binary format? I have some runs taken mistakenly with
xml. |
Wed Nov 25 02:52:35 2015, Chris Thompson, PC software beyond Windows 7
|
I am new to this forum. I have ordered a DRS4 evaluation board for doing experiments with very fast PET detectors. It has not arrived yet. The version
of the manual I downloaded today shows software installation instructions for Windows 7 and earlier versions. I intend to use it on a 64bit PC running
Windows 8.1. Will the Windows 7 driver work, or is there an updated version for Windows 8 or 10? |
Wed Nov 25 17:36:25 2015, Chris Thompson, PC software beyond Windows 7
|
I tried this suggestion of changing the startup settings to ingore driver license signing (as suggested in the post # 434), but when I tried to install
the software I got a error message which I captured from the screen and I have attached. Perhaps I have the wrong version, or, as suggested, the file I
downloaded from your site is incomplete? |
Sat Dec 5 02:39:20 2015, Chris Thompson, PC software beyond Windows 7
|
I tried restarting Windows 10 in a way the allowed me to use "advanced startup options" Option 7 suggested it was to restart without mandatory
driver signing. However, the error persists. Has anyone tested this latest version 5.0.4 on Windows 10? My hardware arrived today, and I am anxious to
test it.!!!! |
Sat Dec 5 03:21:21 2015, Chris Thompson, PC software beyond Windows 7
|
On a hunch, I tried downloading V 5.0.3 instead. This works, and I now have the oscilloscope mode displaying signals! (just to make sure, I re-tire version
5.0.4 and still get the same error. So, in summary V 5.0.3 seems to install successfully and work with Windows 10, but the newer V5.0.4 does not install...
I assmume that I am missing something though, as the newer version is 10 Mbytes bigger! |
Thu Jan 14 21:49:37 2016, Chris Thompson, Triggering of DRS4 in the fastest sampling mode
|
I am attempting to use the DRS4 to measure the timing resolution of a pair of SensL silicon photomultipliers (SiPM). In order to do this I need to trigger
the DRS4 only when there is a coincidence between the two input signals, and hopefully make histograms of the relative detection times of each detector.
There are two completely separate issues. (1) I think this may just be a labelling error. In the first image (OR_mode_selected) one can clearly |
Thu Mar 31 20:48:00 2016, Chris Thompson, Trigger on the And of a positive and negative signal
|
I needed a fast pulse inverter in order to feed signals from the recent SensL SiPMs into a conventional CFD which only accepted negative signals. I got
a very small ferite torridal transformer from Coilcraft and wired up to invert signals then inserted into in 50 ohm coax cable and it works fine. These
things cost only a few cents each! |
Fri Apr 1 22:09:07 2016, Chris Thompson, Trigger on the And of a positive and negative signal
|
The coilcraft part number is: JA4220-ALB. Iordered two of them and they were sent as free samples. You might want to buy some slightly bigger
ones. I found them so small it was very hard to solder the coax cable to the connectors. Since I got them, I managed to damage one as they are quite fragile!
In the confirmation email I got there was some contact info which may be useful for you: "For help, contact Victoria Berner |
Sun Apr 3 22:10:19 2016, Chris Thompson, Trigger on the And of a positive and negative signal
|
No there are no other components. I put a photo of the inverter with its cables SMA and one end, BNC at the other. You can see it is very small. I glued
the inverter to a piece of thin plywood, and fixed the cables to it before attempting to solder them to the pads on the ferite bead support
Abaz |
Fri Jun 27 11:23:19 2014, ChengMing Du, drsosc binary to cern ROOT file conversion
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Stefan Ritt wrote:
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Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage
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Hello Mr. Stefan Ritt
For DRS4 differential inputs ranges form 500mV to 1100mV, with ROFS set to 1.55V, O_OFS set to 1.3V, the outputs of DRS4 is shown in the
attachment. |
Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage
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Here's the problem. My external ADC has 2Vpp differtial input voltage range. And the common-mode voltage of the inputs need to be 1.3V. I cannot
make both the transparent-output and the readout-output meet the ADC input requirement.
Stefan |
Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage
|
I'm using an AD9252, 0.9V common mode voltage is suggested and I already use 8 un-switchable level shifters. Just as you said, this common mode range
is recommended for optimum performance and the device can function over a wider range with reasonable performance. So I think I could
adjust O_OFS to a minor level during transparent output. |
Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage
|
Yes. I use exactly the same scheme as you mentioned. I'll try your solution.
Stefan
Ritt wrote:
There might be a solution. How do you bias th input |
Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage
|
If using a ROFS of 0.9V, the input would not between 1.05V~2.05V better non-linearity area. Is that appropriate?
Stefan
Ritt wrote:
There might be a solution. How do you bias th input |
Mon Jul 20 09:25:38 2015, Chenfei Yang, Measure the time between different samples
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Hi,
I have a question using a data acquisition card base on DRS4 chip. How can I measure the time between several samples of one channel,with the
accuracy of like nanoseconds , for I am using the internal trigger. Is there any complete work about this problem?
|
Tue Apr 15 18:35:41 2014, Carlo Stella, drs_exam project fail to compile
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Hi,
when I try to compile drs_exam project my computer give me this output:
|
Thu Apr 24 23:03:25 2014, Carlo Stella, drs_exam project fail to compile
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Stefan Ritt wrote:
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Sat Jul 13 01:00:15 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello,
I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There
seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or |
Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality
|
Hello Stefan,
Thanks for the quick reply. The issue was a faulty SMA connector, should have checked this first. Signal looks good now.
Thanks for your time, |
Thu Apr 14 18:23:53 2011, Bob Hirosky, Fixes to DOScreen.cpp for recent built on linux
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Hello,
I was just building version 3.1.0 and ran into some problems in DOScreen.cpp. Basically the conversions from
|
Thu Apr 11 22:41:13 2013, Bill Ashmanskas, code/details for optimal DRS4 timing calibration?
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Hi Stefan,
Is either some example code or a detailed written description available for the improved DRS4 timing-calibration algorithm described by Daniel
Stricker-Shaver at MIC 2012? I think you told me that you had verified the results with your own test set-up, so I figure there must be at least |
Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?
|
Hi Stefan,
We have for some time now been using custom firmware on a custom board to read waveforms out of DRS4 chips. Now we are working on cascaded
readout mode, 4 channels @ 2048 samples, WSREG=0x55, in order to allow for longer trigger latency. |
Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?
|
Aha -- many thanks. I think what tripped up my test logic is that the "done" state in drs4_eval5_app.vhd that executes post-readout sets
DWRITE back to 1 (drs_write_set). If one then writes to FPGA register 5 while the FSM is in the "idle" state, the conf_strobe and wsr_strobe
states occur with DWRITE and DENABLE both asserted. This is if one sets the "dactive" bit in the FPGA app code, which is probably not the |
Mon Apr 22 15:33:28 2013, Benjamin LeGeyt, effect of jitter/alignment between SRCLK and ADC clock
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Hello!
let me apologize in advance if this has already been covered somewhere and I missed it.
|
Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode?
|
Hello!
We're developing electronics based on the DRS4 to read out a breast PET scanner and our event rate will be quite high so we're concerned about
dead-time. with that in mind, I have a question regarding the mode of simultaneous writing and reading that is described in the DRS4 data sheet. |
Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate
|
Hi,
Our setup uses a DRS4 evaluation board (version 2.0).
Although we trigger the board at a rate of ~4kHz (on channel2), readout through USB2 is only happening at a rate of ~125Hz. |
Fri Sep 13 15:27:41 2019, Arseny Rybnikov, Scaler / How to modify the firmware to change the scaler integration time
|
Hello,
We want to use the inner DRS4 counter(scaler) within more than the 100ms integration time. We guess that we need to modify the original
firmware around this point: |
Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X
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For the users using a Macintosh,
after several hours the Evaluation Board is working on my Macintosh (intel).
1) install the development package with xcode, its on the OS X installation DVD |
Mon Sep 23 09:22:52 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board
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Is it possible to set sampling frequency at 100 MHz in DRS4 eval board? Trying to set 0.1GHz in Osci program results in around 0.7 GHz. In drscl.exe
i'm able to set freq at 0.1GHz but calibration is impossible.
Thank For Help! |
Mon Sep 23 09:51:48 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board
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Stefan Ritt wrote:
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Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root
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Hello,
I compiled base file for drs system (DRS.cpp) to root framework (root.cern.ch) as dynamic library DRS.so. It can be used for building many
kind of applications under the root system. I applied it for older version of root 5.28 and for latest version 6.02 too. |
Fri Sep 16 22:06:07 2011, Andriy Zatserklyaniy, compilation error for version 4.0.0 on linux
|
Hi Stefan,
When I compiled DRS4 software version 4.0.0 on Linux (Debian Squeeze) I got this compilation error:
g++ -g -O2 -Wall -Wuninitialized -fno-strict-aliasing -Iinclude -DOS_LINUX -DHAVE_LIBUSB -DUSE_DRS_MUTEX musbstd.o mxml.o strlcpy.o DRS.o ConfigDialog.o |
Tue Nov 19 04:33:22 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks
|
I installed Mac OS package on macbook (late 2013). DRSOsc starts to write file but freezes; need to be restarted to restore connection with DRS4
evaluation board (ordered Aug 2011).
When I ran from the command line, I see these messages: |
Tue Nov 19 21:49:37 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks
|
Stefan Ritt wrote:
|
Sat Jun 23 00:29:52 2012, Andrey Kuznetsov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
On the evaluation board, yes. This board is not optimized for high readout rate. If you do your own |
Wed May 8 06:07:52 2013, Andrey Kuznetsov, DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program
|
Hi,
I have an old v2.0 board that I just upgraded firmware on using v4.0.0 download package which has a drs4_eval1.bit for v2.0 boards containing firmware
15158. So I would like to use the latest DRS Oscilloscope program, due to the faster acquisition speeds and advanced calibration techniques, however I |
Wed May 8 19:50:01 2013, Andrey Kuznetsov, DRS4 installation on Windows 8 issues
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I'm also having trouble installing drivers and running DRSOsc program on another computer running Windows 8.
The issue with the driver is that it's not digitally signed. |
Thu Jul 25 01:31:29 2013, Andrey Kuznetsov, Evaluation Board Behavior
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alonzi wrote:
|
Wed Aug 28 13:07:51 2013, Andrey Kuznetsov, Some bug fixes and questions
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For http://www.psi.ch/drs/DocumentationEN/manual_rev20.pdf:
0 0x02 15..8 board_type 5 for DRS4 USB Evaluation Board 1.1 ---> should instead say Evaluation Board 2.0 ?
I've been reviewing DRS.cpp v4.0.1 |
Thu Sep 5 10:01:00 2013, Andrey Kuznetsov, Some bug fixes and questions
|
#11 0x080589de in DRSBoard::GetWave (this=0xb7456008, chipIndex=0, channel=0 '\000', waveform=0x40f24000, responseCalib=true, triggerCell=207, wsr=0,
adjustToClock=false, threshold=1, offsetCalib=true) at src/DRS.cpp:3380
This is calling: |
Mon Sep 9 06:49:36 2013, Andrey Kuznetsov, Some bug fixes and questions
|
The DRSCallback *pcb is missing an if statement in the code when DRS Oscilloscope software isn't used when calibrating in function: int DRSBoard::CalibrateTiming(DRSCallback *pcb) |
Wed Sep 11 02:41:28 2013, Andrey Kuznetsov, USB connection stops
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Hi,
although I don't have a chance to test your code, it looks very similar to what I am using.
|
Thu Jun 20 01:36:48 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the
readout state machine from the evaluation board firmware. |
Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
Thanks so much for clarifying this. We made wait_vdd a parameter controlled by software and will try to experiment with it to find some compromise
between deadtime and the offset added by the droop in VDD. |
Wed Oct 26 21:15:35 2016, Alexey Lubinets, Problems with DRS command line
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Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
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Thu Nov 24 00:40:38 2016, Alexey Lubinets, PLL did not lock
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Hello, everybody!
I installed DRSosc and DRScl. Command line works normally (at least, it can "see" the board). But when I start the oscilloscope, I
have an error: "PLLs did not lock on USB board #0, serial number #...". In Info section I can see the board type = 9 (and in the error message |
Mon Nov 28 16:48:15 2016, Alexey Lubinets, PLL did not lock
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The serial number is 2586. This board is about two years old, and it might be in use (but I do not know exactly).
Stefan
Ritt wrote:
Which serial number has the board? Has it been in use before or is it |
Thu Dec 17 09:29:43 2020, Alex Myczko, drs sources on github?
|
Are there plans to add the drs software to github? (asking because I have users @ethz.ch that want to use it on debian,
thus I'm creating official debian packages of it, if license allows so, but talking to upstream (the developers) would be
much easier on github (or irc) than on this "DRS4 Discussion Forum".
|
Tue Feb 15 11:59:22 2022, Alex Myczko, apt install drs4eb
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drs4b is now officially on these distributions:
https://repology.org/project/drs4eb/versions
enjoy |
Fri Apr 13 18:14:07 2018, Alessio Berti, Voltage and Timing Calibration in drs_exam.cpp
|
Hi,
we were trying to implement an automatic way to calibrate our DRS4 both in voltage and in time (we have the V5 Evaluation Board). We started
from drs_exam.cpp and tried with the following lines: |
Wed May 2 10:44:17 2018, Alessio Berti, Peak at 0 mV in traces
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Hi,
we modified drs_exam.cpp to read all 4 channels from the DRS4 and apply directly the spike removal (taken from Osci.cpp) during the acquisition
phase. For test purposes, we don't save the data showing spikes and we focus on the data not having spikes (even if at the end we end up having triple |
Wed May 2 12:23:16 2018, Alessio Berti, Peak at 0 mV in traces
|
Hi,
thank you for the quick reply. All the bins in the previous histograms have the same width. We also tried to plot the noise histogram for channel
2 with more bins (i.e. 1000, so that we can see almost discrete values), and the peak is still there. |
Tue May 8 12:15:54 2018, Alessio Berti, Peak at 0 mV in traces
|
Hi Stefan,
following your example, we tried to perform the same measurement, using drs_exam and taking 1000 events. The results we obtained are in the plots
attached (both in log and linear scale). We tried two different binnings: |
Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED
|
Hi,
I have a machine with Windows 10 and the solution provided by Steven works fine. To give more details, the driver installed in my case is WinUSB
(i.e. libusb, v6.1.7600.16385). |
Wed May 9 14:07:10 2018, Alec Shackleford, WIndows Connection problem with drs507 SOLVED
|
Thank you for this fantastic solution. I had almost reinstalled windows 7 to see if that would solve the issue!
All the best, |
Tue Sep 10 10:31:30 2013, Akira Okumura, USB connection stops
|
Hello the DRS4 team,
I and some of my colleagues are using DRS4 evaluation boards (ver. 3) for the R&D of the Cherenkov Telescope Array project. During
|
Wed Sep 25 14:42:00 2013, Akira Okumura, USB connection stops
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Hello Andrey,
Thank you for your advise. But we never terminated the program before closing and deleting the DRS object. What we did was just executing the program multiple |
Mon Mar 23 15:03:28 2020, Ajay Krishnamurthy, USB trigger issue
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Hello,
I had forgotten to disable the turn off the power to the USB drive on Windows and DRS4 stopped triggering. Now, we are all on quarantine and
I am unable to reset the board to normal function. Are there any commands to reset the board remotely. I tried all of the default Windows based solutions |
Thu Nov 10 04:41:24 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro
|
Hello,
I recently modified the binary to ROOT convertor written by Stefan (https://midas.psi.ch/elogs/DRS4+Forum/361) so it can decode data taken
with any channel or set of channels on the DRS4. In the process of testing this modifed version for data taken on all 4 channels, I encountered problems |
Thu Nov 10 19:24:52 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro
|
Hello,
I am wondering why the code should be changed to i < sizeof(eh), since doesn't fread(&eh,sizeof(eh),1,f) return 1 in this scenario?
I've confirmed with a cout statement that this is the case, so this break condition will therefore always trigger as sizeof(eh) is 32 bytes. |
Wed Nov 23 08:17:23 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
|
Hello,
I was running through a particular binary file containing data taken on all 4 channels of the DRS4 and printing out the value of the first time
sample for each channel (per event). While doing so, I noticed that some of these times were negative. For this dataset, channel 1 was chosen |
Tue Nov 29 23:19:06 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
|
Hello Stefan,
Thank you for the excellent explanation and diagram. This part of the code is now much clearer to me.
My other questions pertain to the "trigger cell". Firstly, what precisely does this mean? Moreover, how does the "trigger |
Fri Dec 9 04:17:46 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
|
Hello Stefan,
Many thanks for the explanations. You've cleared my confusion in this matter.
Abhishek Rajput |
Thu Mar 31 19:30:26 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
|
I would like to be able to trigger in this fashon: channel 0 > 0.1 and. channel 1< -0.1, because I have a positive and a negative signal.
Can DRS4 (5) Eval board do this kind of trigger?
Thanks! |
Thu Mar 31 19:44:38 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
|
Ok, thanks! do you know an easy in-line inverter like mini-circuit or digikey? Can also redesign the detector I gues to produce
positive signals, just it might be easier if there was a simple inverter if you are aware of? thanks Abaz
Stefan |
Thu Mar 31 20:38:05 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
|
Thanks, that looks just fine.
Stefan
Ritt wrote:
Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups |
Fri Apr 1 01:30:40 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
|
Hi Chris,
I am looking at Sensl SiPMs as well, can you send the part number from Coilcraft?
Thanks! |
Sat Apr 2 17:22:34 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
|
Thanks again, this is very useful, just another question did you put any other passive elements in the circuit for inverting the signal
or just simply swaped the transformer connections?
Chris |
Sun Apr 3 22:34:28 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
|
Thanks, great!
Chris
Thompson wrote:
No there are no other components. I put a photo of the inverter |
Wed Apr 27 20:04:12 2016, Abaz Kryemadhi, Best settings for time measurements
|
I am studing some pulses that are about 200-300 ns wide and a rise time of few ns, which settings would be best for coincidence time
measurements?
In some preliminary work I found for 700 MegaS the time measurement is better without time calibration (in -0.05 to 1V) rather than with time |
Tue Jan 29 14:43:44 2019, Abaz Kryemadhi, ROOT Macro for data acquired with the newest software
|
Hello,
Is there a root macro for decoding binary data acquired with the newest software for single board or multi-boards daisy chained?
Cheers, |
Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software
|
The older root macro did not work for me for data acquired with the newest software.
so for the newest software and multiple boards, I modified the read_binary.cpp into read_binary.C for those who like to use the root macro, see
the attachment. |
Tue May 4 21:18:28 2021, Abaz Kryemadhi, recording only timestamp and amplitude and/or filesize maximum
|
Hi,
I have been collecting some date using the DRS4 board at a trigger rate of 10-20 Hz, I only need the timestamp and the amplitude,
is there anyway to select only these two live as the data comes in to be stored. |