ID |
Date |
Author |
Subject |
Text |
|
909
|
Fri Jun 28 23:33:51 2024 |
Patricia Lecomti | Error when running drsosc | Salut !
Je vois que tu rencontres un petit
problème avec ton installation. Le |
|
908
|
Tue May 21 18:13:08 2024 |
Rebecca Hicks | Error when running drsosc | Hi, I'm a student trying to figure
out the DRS4 board. I cloned the github repo,
but when I run drsosc, I get an error: Gtk-Message: |
|
907
|
Thu Feb 22 10:37:03 2024 |
Stefan Ritt | Simulation of FPGA | The Cypress has its own firmware, contained
in the distribution under firmware/CY7C68013A/drs_eval.c.
There you can see how the data is fetched. |
|
906
|
Thu Feb 22 01:21:11 2024 |
Rod McInnis | Simulation of FPGA | Hello:
A bit of background: I am
working on a project that is utilizing the |
|
905
|
Wed Oct 25 19:52:33 2023 |
John Westmoreland | WaveDREAM Design | Stefan,
Oh, didn't realize that.
Thanks! |
|
904
|
Wed Oct 25 19:47:23 2023 |
Stefan Ritt | WaveDREAM Design | No. This is a proprietary design.
Best,
Stefan |
|
903
|
Wed Oct 25 19:44:25 2023 |
John Westmoreland | WaveDREAM Design | Hello All,
Are there any design resources
available for the WaveDREAM PCBA's? |
|
902
|
Wed Sep 13 13:18:45 2023 |
Stefan Ritt | Input range switch added in Version 2.1.3 | To achieve an input range of -1V to 0V,
you need an external buffer which can shift
this range into the DRS4 range of -0.5V to |
|
901
|
Tue Sep 5 03:28:52 2023 |
Matias Henriquez | Input range switch added in Version 2.1.3 | Hello,
It is not quite clear to me yet
how the input range is only determined by |
|
899
|
Mon Jun 12 14:22:04 2023 |
Stefan Ritt | Different sampling rates in multi-board configuration | No, that's unfortunately not possible.
Stefan
|
|
898
|
Fri Jun 9 04:11:40 2023 |
Javier Caravaca | Different sampling rates in multi-board configuration | Hello,
Is it possible to have different sampling
rates in multi-board configuration? I tried |
|
897
|
Mon Feb 6 13:28:28 2023 |
Stefan Ritt | DRS4 installation via tar in ubuntu not working | I fixed the described error. Can you try
the new version from https://bitbucket.org/ritt/drs4eb/commits/80b3af753ed32eb365725f0f3244a4109347c01b
|
|
896
|
Mon Oct 24 12:50:24 2022 |
Stefan Ritt | Channel Cascading Option in the 2048-bin | The board is delivered in one or the other
mode and not meant to be changed by the user,
since this requires very delicate soldering |
|
895
|
Sat Oct 22 13:24:20 2022 |
Phan Van Chuan | Channel Cascading Option in the 2048-bin | Dear Stefan,
We are using DRS4 evaluation board
version 5.1 and firmware version 30000 (as |
|
894
|
Mon Oct 17 16:29:37 2022 |
Sebastian Infante | DRS4 installation via tar in ubuntu not working | Hello i cant install any the last versions
that i downloaded from the dropbox, i can
untar the file called drs-5.0.6 and when |
|
893
|
Tue Sep 27 15:20:55 2022 |
Stefan Ritt | Required Firmware for DRS4 Evaluation Board Version 2.0 | Sorry, got the wrong link. Here the right
one: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
If you untar the archive, you will |
|
892
|
Tue Sep 27 10:52:41 2022 |
Kunal Shinde | Required Firmware for DRS4 Evaluation Board Version 2.0 | I checked the link you provided but it
seems that the link doesnt exist please send
me valid one. |
|
891
|
Tue Sep 27 10:37:11 2022 |
Stefan Ritt | Required Firmware for DRS4 Evaluation Board Version 2.0 | You find each software version at the usual
download location at
https://www.dropbox.com/home/drs/drs4/distribution/Download/Linux |
|
890
|
Tue Sep 27 10:17:58 2022 |
Kunal Shinde | Required Firmware for DRS4 Evaluation Board Version 2.0 | Hi, I am working on an old DRS4 board Version
"2.0" with firmware revision "13191",
I was unable to find this specific firmware |
|
889
|
Wed Sep 7 10:13:41 2022 |
Prajjalak Chattopadhyay | Register status after reset | What are the default register statuses
after DRS4 gets reset? |
|
888
|
Fri Jul 29 17:23:43 2022 |
Stefan Ritt | Spikes/noise sensitive to clock settings? | Look at the DRS4 data sheet, Figure 12.
You see there the rising SRCLK pulse which
outputs the next analog value. You also see |
|
887
|
Fri Jul 29 14:09:35 2022 |
Stefan Ritt | Increase event rate, use ROI mode, and install sw from source in Mac | The firmware from the website always reads
1024 bins. You have to modify it to stop
before that, like reading only 128 samples |
|
886
|
Tue Jul 19 02:35:04 2022 |
Jingyu Zhang | Increase event rate, use ROI mode, and install sw from source in Mac | Dear
experts,
|
|
885
|
Fri Jun 24 09:57:36 2022 |
LynseyShun | Spikes/noise sensitive to clock settings? | Hello, I now have periodic spikes in CH0
and CH1 output. How can I eliminate
these spikes? I'm sorry I didn't |
|
884
|
Thu Jun 16 05:31:25 2022 |
LynseyShun | | Thank you very much for your help!
|
|
883
|
Tue Apr 12 10:49:27 2022 |
Stefan Ritt | | A3-A0 = 1001 should be all you need to
activate OUT0-OUT7. It works in our designs.
Maybe double check the address lines with |
|
882
|
Tue Apr 12 10:40:36 2022 |
LynseyShun | | Hello, I am Lynsey. now I set A3-A0 to
1001 in ROI mode, but only OUT0 has output,
and the other seven channels(OUT1-OUT7) do |
|
881
|
Tue Mar 15 13:07:50 2022 |
Matias Senger | Time calibration and the C++ API | Thanks for your help. If I look into the
app the behavior for the 4 channels is exactly
as you show: |
|
880
|
Mon Mar 14 08:59:51 2022 |
Stefan Ritt | Time calibration and the C++ API | Looks like you have the some time calibration,
not sure if it's the correct one. Sample
the sine wave from the calibration clock, |
|
879
|
Sat Mar 12 16:52:36 2022 |
Matias Senger | Time calibration and the C++ API | Dear Stefan,
For the time of each bin I am using
the values returend by `GetTime` without |
|
878
|
Sat Mar 12 10:13:24 2022 |
Stefan Ritt | Time calibration and the C++ API | DRSBoard::GetTime is declared in DRS.h
line 720.
If you want to measure timing down |
|
877
|
Fri Mar 11 17:26:15 2022 |
Matias Senger | Time calibration and the C++ API | I am using the V5 board at a fixed sampling
frequency. With the `drsosc` app I have executed
the time calibration at 5 GS/s (actually |
|
876
|
Tue Mar 8 12:20:00 2022 |
Matias Senger | Why does not trigger at higher sampling frequencies? | Sorry for the spam. Just want to let you
know that I was able to solve the problem,
it was all due to a `float` being casted |
|
875
|
Tue Mar 8 00:25:56 2022 |
Matias Senger | Why does not trigger at higher sampling frequencies? | I have seen in the app that the trigger
source buttons do something different than
the "or" and "transparent |
|
874
|
Mon Mar 7 16:37:54 2022 |
Stefan Ritt | Scaler issue to evaluate live time | I tried your measurement with the DRSOscilloscope
app (see below), and I measure a constant
difference of 10 Hz among the whole range |
|
873
|
Mon Mar 7 13:38:03 2022 |
Radoslaw Marcinkowski | Problems with DRS4 Evaluation Board after Windows 10 upgrade - share of experiences | Dear DRS4 Users,
I would like to share my expireinces
with using of DRS4 Evaluation Board software |
|
872
|
Mon Mar 7 08:45:32 2022 |
Stefan Ritt | Why does not trigger at higher sampling frequencies? | Unfortunately I have not idea what the
problem could be. In principle the trigger
should be independent of the sampling speed, |
|
871
|
Sun Mar 6 17:54:47 2022 |
Matias Senger | Why does not trigger at higher sampling frequencies? | I have connected 3 signals to the DRS4
Evaluation Board V5 which look like this
in the drsosc app: |
|
870
|
Fri Mar 4 03:55:33 2022 |
Keita Mizukoshi | Scaler issue to evaluate live time | Thank you very much for your explanation.
I would like to show you a pulse |
|
869
|
Thu Mar 3 16:14:16 2022 |
Stefan Ritt | Scaler issue to evaluate live time | The scalers are read out 10x per seconds,
so they have an accuracy of 10 Hz. I tried
a 50 Hz pulser, and measured 40 Hz, I tried |
|
868
|
Thu Mar 3 13:47:26 2022 |
Stefan Ritt | How to convert samples to volt? | The 'drscl' tool is more for experts,
normal users are advised to use the DRSOsc
oscilloscope. |
|
867
|
Wed Mar 2 17:25:10 2022 |
Matias Senger | How to convert samples to volt? | I am using the `drscl` app. My prior experience
is practically zero, sorry if this is a very
naive question. When I read using `read 0 |
|
866
|
Tue Mar 1 19:03:37 2022 |
Keita Mizukoshi | Scaler issue to evaluate live time | Hi. I'm trying to evaluate livetime
of the evaluation board with the hardware
scaler. I'm facing a strange issue. |
|
865
|
Wed Feb 16 14:06:45 2022 |
Dmitry Hits | Sliders missing in drsosc | Hi everyone,
Did anyone have a "missing
sliders problem" in GUI (see attachment) |
|
864
|
Tue Feb 15 12:02:29 2022 |
Stefan Ritt | Cannot trigger on pulses, have to trigger on undershoot | The trigger comparator is a ADCMP601 unit
which requires a minimum pulse width of 3-4
ns. I see that your pulses are only 1-2 ns |
|
863
|
Tue Feb 15 11:59:22 2022 |
Alex Myczko | apt install drs4eb | drs4b is now officially on these distributions:
https://repology.org/project/drs4eb/versions
enjoy |
|
862
|
Sat Feb 12 13:06:56 2022 |
Matias Senger | Cannot trigger on pulses, have to trigger on undershoot | I am using the DRS4 board trying to measure
pulses produced by an LGAD. I have no prior
experience with this board, have just installed |
|
861
|
Wed Jan 26 06:44:11 2022 |
student_riku | I want to know about the readout | Dear Stefan
Thanks a lot.
I solved it. |
|
860
|
Tue Jan 25 14:44:49 2022 |
Thomas M. | Regarding measuring for a set time | Yes, you've got it exactly right. Thank
you, that helps a lot!
Thomas |
|
859
|
Tue Jan 25 14:34:42 2022 |
Stefan Ritt | Regarding measuring for a set time | drsosc is a graphical application contiously
acquiring data from the board, and drscl
is a command line tool for debugging, as |
|
858
|
Tue Jan 25 14:15:00 2022 |
Thomas M. | Regarding measuring for a set time | Hello,
I'm working on a project wherein
we're looking at photomultipliers. We've |
|
857
|
Sat Jan 15 10:50:47 2022 |
Stefan Ritt | I want to know about the readout |
student_riku |
|
856
|
Sat Jan 15 09:13:42 2022 |
student_riku | I want to know about the readout | Hello, everyone.
I'm a student in Japan.
Please forgive me if this is a very |
|
855
|
Mon Jan 3 17:13:41 2022 |
Stefan Ritt | DRS4 request assistance | 1. fDOMINO is defined as fREFCLK * 2048
2. Good values can be derived from
the evaluation board schematics: C1=4.7nF, |
|
854
|
Fri Dec 24 03:13:32 2021 |
Lynsey | Trouble getting PLL to lock | I also design the circuit myself. Our problem
is the same. Can we communicate?
|
|
853
|
Thu Dec 23 03:42:26 2021 |
Lynsey | DRS4 request assistance | Dear Sir or Madam,
Good morning,I
am using drs4 chip, and the measured fDTAP |
|
852
|
Tue Nov 16 08:51:14 2021 |
Stefan Ritt | V3 board, only one channel works, all components at each channel input working | A V3 boards is already 10 years old and
out of warranty. The software has no configuration
to turn channels off except the channel buttons |
|
851
|
Tue Nov 16 01:27:51 2021 |
Jacquelynne Vaughan | V3 board, only one channel works, all components at each channel input working | Hi everyone,
I'm still looking through the
forum for an answer to this question, but |
|
850
|
Fri Nov 5 01:12:10 2021 |
Jiaolong | how to acquire the stop channel with 2x4096 cascading | Thanks for your advice. The problem has
been solved by setting the srin again while reading
out from srout. |
|
Draft
|
Fri Nov 5 01:10:25 2021 |
Jiaolong | how to acquire the stop channel with 2x4096 cascading |
|
|
848
|
Wed Oct 27 08:11:42 2021 |
Stefan Ritt | Trigger multiple boards independently | I'm not sure if the rate would go up
to 2 kHz (not 2 GHz!). Depends how the USB
hub is designed. What you can do however |
|
847
|
Tue Oct 26 23:18:32 2021 |
Javier Caravaca | Trigger multiple boards independently | Thank you Stefan. Actually I noticed that the
source code of drs_exam was available after
I started this thread, and that was the solution |
|
846
|
Tue Oct 26 15:05:18 2021 |
Mehrpad Monajem | External trigger and drs_exam | Thanks for your reply.
1- I want to have a window size
of 25.6ns instead of 200ns at 5GSPS. I have |
|
845
|
Tue Oct 26 12:02:56 2021 |
Stefan Ritt | Trigger multiple boards independently | Unfortunately an independent operation
from a single computer is not supported by
the software. You can try to modify the drs_exam |
|
844
|
Tue Oct 26 12:00:51 2021 |
Stefan Ritt | External trigger and drs_exam | 1. Why should your waveform start from
0 to 5ns? I don't get your point. Whenever
you trigger a readout, you get a 200ns wide |
|
843
|
Tue Oct 26 10:41:46 2021 |
Mehrpad Monajem | External trigger and drs_exam | Hi Stefan,
I have two problems regarding using |
|
842
|
Mon Oct 25 18:48:04 2021 |
Javier Caravaca | Trigger multiple boards independently | Hello,
I recently acquired 4 DRS4 boards
and I wanted to ask if it was possible to |
|
841
|
Fri Oct 15 06:15:53 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board | Thank you very much.
|
|
840
|
Thu Oct 14 18:42:31 2021 |
Stefan Ritt | livetime (or deadtime) of DRS4 evaluation board | I would say not exactly, but it's a
good approximation.
|
|
839
|
Thu Oct 14 18:03:52 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board | Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the |
|
838
|
Thu Oct 14 15:25:07 2021 |
Stefan Ritt | livetime (or deadtime) of DRS4 evaluation board | The one thing you can do easily is to look
at the scaler values. If one channel counts
all physical events, and you have all read |
|
837
|
Thu Oct 14 15:19:00 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board | Dear experts,
I would like to use the DRS4 evaluation |
|
835
|
Sat Sep 18 15:48:30 2021 |
Stefan Ritt | drs_exam_multi with non-v4 boards, default configuration | Hi,
please note the the evaluation
board is what it says, a board to evaluate |
|
834
|
Sat Sep 18 15:47:50 2021 |
Stefan Ritt | how to acquire the stop channel with 2x4096 cascading | The problem must be on your side, since
the Write Shift Register readout works in
other applications with the DRS4 chip. So |
|
833
|
Thu Sep 16 19:04:06 2021 |
Patrick Moriishi Freeman | drs_exam_multi with non-v4 boards, default configuration | Hello,
I made a modified version drs_exam_multi.cpp,
but ran into an issue when running. When |
|
832
|
Mon Sep 6 14:42:23 2021 |
Jiaolong | how to acquire the stop channel with 2x4096 cascading | Hi Steffan,
I have a question
about how to acquire the stop channel: |
|
831
|
Tue Aug 10 13:57:09 2021 |
Mehrpad Monajem | C code to read the 4 channel with external trigger | Thank you for the reply.
In the version that I have, I cannot
find drs_exam_2048.cpp file. Could you please |
|
830
|
Mon Aug 9 12:50:31 2021 |
Stefan Ritt | C code to read the 4 channel with external trigger | Sorry the late reply, I was on vacation.
Here are some answers:
1. I'm sorry I can't help |
|
829
|
Wed Jul 14 14:55:09 2021 |
Mehrpad Monajem | C code to read the 4 channel with external trigger | Hi there,
Recently I bought a 5GSPS evaluation
board with 2048 sampling points. |
|
828
|
Wed May 5 10:12:44 2021 |
Stefan Ritt | recording only timestamp and amplitude and/or filesize maximum | The maximum file size depends on the underlying
linux file system. Common values are 4-16
GBytes. |
|
827
|
Tue May 4 21:18:28 2021 |
Abaz Kryemadhi | recording only timestamp and amplitude and/or filesize maximum | Hi,
I have been collecting some date
using the DRS4 board at a trigger rate of |
|
826
|
Fri Apr 9 21:56:54 2021 |
Sean Quinn | Unexpected noise in muxout: t_samp related? | Yes, there is some systematic board noise
on this prototype, unfortunately |
|
825
|
Fri Apr 9 21:38:59 2021 |
Stefan Ritt | Spikes/noise sensitive to clock settings? | elog:824
|
|
824
|
Fri Apr 9 20:55:28 2021 |
Stefan Ritt | Unexpected noise in muxout: t_samp related? | If you do the cell calibration correctly,
your noise should be ~0.4 mV. You seem to
be 2-3x larger. The periodic negative spikes |
|
823
|
Fri Apr 9 20:29:45 2021 |
Sean Quinn | Spikes/noise sensitive to clock settings? | Dear DRS4 team,
I'm trying to troubleshoot
some odd spike behavior. If I run the ADC |
|
822
|
Fri Apr 9 20:22:13 2021 |
Sean Quinn | Unexpected noise in muxout: t_samp related? | Hi Stefan,
Thanks much for the quick reply. |
|
821
|
Wed Apr 7 08:26:12 2021 |
Stefan Ritt | Unexpected noise in muxout: t_samp related? | Dear Sean,
noise in transparent mode comes
from some coupling to your system clock. |
|
820
|
Wed Apr 7 03:29:39 2021 |
Sean Quinn | Unexpected noise in muxout: t_samp related? | Dear DRS4 team,
I'm experiencing some issues
that seem to be isolated to the ASIC, and |
|
819
|
Fri Mar 5 09:39:42 2021 |
Stefan Ritt | Trouble getting PLL to lock | That probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock |
|
818
|
Thu Mar 4 21:36:14 2021 |
Tom Schneider | Trouble getting PLL to lock | I found the problem, and it had nothing
to do with the CMOS clock input. As
it turns out, even though I was using the |
|
817
|
Fri Feb 26 22:52:13 2021 |
Tom Schneider | Trouble getting PLL to lock | Thats not a simple modification to my PCB,
but I'll give it a try. Thanks
for your help |
|
816
|
Fri Feb 26 22:12:58 2021 |
Stefan Ritt | Trouble getting PLL to lock | Sounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals |
|
815
|
Fri Feb 26 21:24:39 2021 |
Tom Schneider | Trouble getting PLL to lock | Probe capacitance makes that tricky - if
I put my probe on DSPEED, I see that it starts
at approx. 2.5V then gradually decreases |
|
814
|
Fri Feb 26 20:32:25 2021 |
Stefan Ritt | Trouble getting PLL to lock | Can you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?
|
|
813
|
Fri Feb 26 18:33:52 2021 |
Tom Schneider | Trouble getting PLL to lock | Stefan,
Thanks for responding so quickly.
Yes I have my clock source going to REFCLK+ |
|
812
|
Fri Feb 26 17:59:14 2021 |
Stefan Ritt | Trouble getting PLL to lock | I guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else! |
|
811
|
Fri Feb 26 17:05:26 2021 |
Tom Schneider | Trouble getting PLL to lock | Hello,
I am working on a custom PCB design
with the DRS4 chip, and I can't get the |
|
810
|
Fri Feb 26 08:52:50 2021 |
Stefan Ritt | DRS spike removal for multiple waveforms | Just look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid |
|
809
|
Thu Feb 25 17:56:39 2021 |
Matthias Plum | DRS spike removal for multiple waveforms | Hi,
Is there a way that someone can
help me and my student to enable RemoveSymmetricSpikes |
|
808
|
Wed Jan 20 17:37:51 2021 |
Stefan Ritt | drs4 persistence | The chip itself can only sample a single
waveform, that must be done in the attached
software. The current DRSOscilloscope software |
|
807
|
Wed Jan 20 12:14:49 2021 |
Taegyu Lee | drs4 persistence | Dear all,
I have a question about the function that
drs4 can perform. |
|
806
|
Thu Dec 17 11:31:34 2020 |
Stefan Ritt | drs sources on github? | Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/
But development kind of stalled, so there |
|
805
|
Thu Dec 17 09:29:43 2020 |
Alex Myczko | drs sources on github? | Are there plans to add the drs software to
github? (asking because I have users @ethz.ch
that want to use it on debian,
|
|
804
|
Wed Oct 28 04:32:19 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
OK, it's good to hear! Thank you! |
|
803
|
Tue Oct 27 15:24:38 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | This is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just |
|
802
|
Tue Oct 27 15:02:09 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
Thank you for your reply. |
|
801
|
Tue Oct 27 13:37:23 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Seiya,
1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure |
|
800
|
Wed Oct 21 15:03:13 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
I have questions about the timing |
|
799
|
Wed Oct 7 11:17:52 2020 |
Elmer Grundeman | External triggering | I will try that, thanks!
|
|
798
|
Wed Oct 7 10:56:03 2020 |
Stefan Ritt | External triggering | The trigger is there only to trigger the
chip, but cannot be used as a precise time
reference. If you want to measure precise |
|
797
|
Tue Sep 22 17:45:26 2020 |
Elmer Grundeman | External triggering | Dear all,
I had a question about timing jitter
and external triggering. |
|
796
|
Mon Aug 31 17:17:30 2020 |
Stefan Ritt | Channel Cascading | If you have a board with cascading option,
it should show the "combined" option
in the 2048-bin option enabled (not grayed), |
|
795
|
Mon Aug 31 16:44:12 2020 |
Hans Steiger | Channel Cascading | Dear All,
I have a board with Channel Cascading
Option. I have the problem, that it seems |
|
794
|
Mon Aug 31 10:52:42 2020 |
Stefan Ritt | Dynamic Range Evaluation Board and Software | You cannot go below -0.5V for the inputs,
since the board does not have an internal
negative power supply, which would be necessary |
|
793
|
Sat Aug 29 22:00:30 2020 |
Hans Steiger | Dynamic Range Evaluation Board and Software | Dear Evaluation Board Team,
currently I am facing the problem |
|
792
|
Tue Jul 28 22:40:44 2020 |
Razvan Stefan Gornea | no board found | I have a very similar problem, the command
line doesn't work but the oscilloscope
program does! Tried to fix it using Zadig |
|
791
|
Tue May 26 12:44:16 2020 |
Stefan Ritt | Domino wave | Look at the attached picture. For simplicity,
only 4 cells are open and tracking the input
signal. Time is flowing from top to bottom. |
|
790
|
Tue May 26 11:10:27 2020 |
xggg | Domino wave | Hi Stefan,
According to the datasheet DRS_rev09,
the write signal is always 16 cells wide. |
|
789
|
Mon May 25 03:36:12 2020 |
Keita Mizukoshi | DRS4 Evaluation board control tool 'drscl' with macro file | Thank you very much. That is what I wanted.
|
|
788
|
Fri May 22 13:24:51 2020 |
Stefan Ritt | Type check at DOFrame.h in official software | The software is a bit outdated, I will
soon make a new release.
In meantime, you can replace that |
|
786
|
Fri May 22 12:53:33 2020 |
Stefan Ritt | DRS4 Evaluation board control tool 'drscl' with macro file | There is an example program in the distribution
under software/drscl/drs_exam.cpp which is
a stand-alone program to do what you need. |
|
785
|
Thu May 21 07:38:05 2020 |
Keita Mizukoshi | Type check at DOFrame.h in official software | Hi,
I've failured to compile official |
|
784
|
Thu May 21 07:18:48 2020 |
Keita Mizukoshi | DRS4 Evaluation board control tool 'drscl' with macro file | Dear experts,
I would like to use DRS4 evaluation |
|
783
|
Mon Mar 23 15:03:28 2020 |
Ajay Krishnamurthy | USB trigger issue | Hello,
I had forgotten to disable the
turn off the power to the USB drive on Windows |
|
782
|
Fri Oct 25 16:39:07 2019 |
Stefan Ritt | Computing corrected time from binary data...what is t_0,0? | t0,0 refers to the time of cell #0 of channel
#0. So basically you keep channel 0 fixed,
calculate the difference of each channel's |
|
781
|
Wed Oct 23 17:56:26 2019 |
John Jendzurski | Computing corrected time from binary data...what is t_0,0? | In the equations for computing the corrected
time for channels other than channel 1, does
anyone know what the term t0,0 refers |
|
780
|
Tue Oct 15 08:14:17 2019 |
Danyang | how to acquire the stop position with channel cascading | Thanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.
Best Regards, |
|
779
|
Mon Oct 14 15:27:09 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | If you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT |
|
778
|
Mon Oct 14 13:44:26 2019 |
Danyang | how to acquire the stop position with channel cascading | Yes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b, A3-A0 |
|
777
|
Mon Oct 14 12:56:13 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | Note that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins |
|
776
|
Mon Oct 14 11:45:06 2019 |
Danyang | how to acquire the stop position with channel cascading | I tried the
logic in my designed board. The results
are shown in the picture: Srout keeps low |
|
775
|
Mon Oct 14 10:14:46 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | You first set A3-A0, on the next clock
cycle you issue pulses on srclk, and about
10ns after each clock pulse the output shows |
|
774
|
Mon Oct 14 09:32:33 2019 |
Danyang | how to acquire the stop position with channel cascading | Hi Steffan,
In DSR4
DATASHEET Rev.0.9 Page13, there is |
|
773
|
Fri Sep 13 15:27:41 2019 |
Arseny Rybnikov | Scaler / How to modify the firmware to change the scaler integration time | Hello,
We want to use the inner DRS4 counter(scaler)
within more than the 100ms integration |
|
772
|
Tue Aug 27 09:14:03 2019 |
Stefan Ritt | DRS4 | Is a 5 GSPS oscilloscope suitable for use
with Silicon surface barier detectors?
|
|
771
|
Tue Aug 27 08:33:22 2019 |
chinmay basu | DRS4 | Is DRS4 suitable for use with Silicon surface
barrier detectors? |
|
770
|
Tue Aug 20 16:05:21 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Aha -- many thanks. I think what
tripped up my test logic is that the "done"
state in drs4_eval5_app.vhd that executes |
|
769
|
Tue Aug 20 10:44:45 2019 |
Stefan Ritt | should one deassert DENABLE while writing the write-shift register? | Hi Bill,
you keep DENABLE active all the
time to keep the Domino Wave running, but |
|
768
|
Mon Aug 19 23:01:22 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Hi Stefan,
We have for some time now been
using custom firmware on a custom board to |
|
767
|
Sat Jul 20 12:28:14 2019 |
Stefan Ritt | Trace Impedance | The DRS4 input is high impedance. So if
you like you can terminate it with 100 Ohm
differentially and route it with 100 Ohm. |
|
766
|
Fri Jul 19 01:37:09 2019 |
Ismael Garcia | Trace Impedance | When you're refering to laying a 50
Ohm trace, you're referring to the SMA
input and not the interface between the output |
|
765
|
Thu Jul 18 11:37:56 2019 |
Stefan Ritt | Trace Impedance | The requiremnet is the same as for any
high speed analog board, there is othing
special with the DRS4. If you want to terminate |
|
764
|
Thu Jul 18 01:03:44 2019 |
Ismael Garcia | Trace Impedance |
Hi Steffan,
|
|
763
|
Mon Jul 15 19:34:25 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello Stefan,
Thanks for the quick reply. The
issue was a faulty SMA connector, should |
|
762
|
Mon Jul 15 17:26:50 2019 |
Stefan Ritt | Evaluation Board Test Functionality | Have you set the trigger correctly to the
channel with your signal, polarity and level?
Do you undersand the difference between normal |
|
761
|
Sat Jul 13 01:00:15 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello,
I have recently obtained a DRS4
Evaluation Board (V5), but I am unable to |
|
760
|
Mon Jul 8 14:29:12 2019 |
Stefan Ritt | drs_exam is always reading out a sin wave | Actually in the original drs_exam.cpp the
sine wave oscillator is turned off with this
command |
|
759
|
Wed Jun 26 15:17:51 2019 |
Si Xie | Running drs_example.cpp | Hi Rodrigo, I'm wondering how you solved
your original triggering problem. We are
also having trouble with collecting data |
|
758
|
Wed Jun 26 15:10:09 2019 |
Si Xie | drs_exam is always reading out a sin wave | I see. Where is the code that we can use
to turn off the generator? I thought the
example is taking data with CH1 as the trigger. |
|
757
|
Wed Jun 26 13:08:42 2019 |
Stefan Ritt | drs_exam is always reading out a sin wave | Sure, that’s correct. The example
program turns on the internal sine wave generator
in case people don’t have a real signal. |
|
756
|
Tue Jun 25 23:04:29 2019 |
Si Xie | drs_exam is always reading out a sin wave | We are using the drs_exam.cpp to read out
waveforms, but it seems to be outputting
only sin waves on all channels - as if it |
|
755
|
Mon Jun 24 23:07:35 2019 |
Andrew Peck | Evaluation firmware wait_vdd state | Dear Stefan,
Thanks so much for clarifying this.
We made wait_vdd a parameter controlled by |
|
754
|
Fri Jun 21 12:54:47 2019 |
Stefan Ritt | Evaluation firmware wait_vdd state | Dear Andrew,
the posting you mention is still
accurate. Any power supply will drop when |
|
753
|
Thu Jun 20 01:36:48 2019 |
Andrew Peck | Evaluation firmware wait_vdd state | Dear Stefan,
I am working with others at UCLA
on a custom made board built around the DRS4. |
|
752
|
Fri Apr 12 12:50:18 2019 |
Stefan Ritt | multi-board | If you have two signal going through two
cables, the cable have never the same length
(on a scale of picoseconds), and you have |
|
751
|
Fri Apr 12 09:59:15 2019 |
Lev Pavlov | multi-board |
I understand this, thanks. But
my Chief does not understand this, he wants |
|
750
|
Fri Apr 12 09:55:50 2019 |
Stefan Ritt | multi-board | Subtract 16 ns from your measured value
;-)
Stefan |
|
749
|
Fri Apr 12 09:39:30 2019 |
Lev Pavlov | multi-board |
Good afternoon, I use 5 boards in
multi-mode, everything is connected according
to the instructions. Can I measure the phase |
|
748
|
Thu Mar 14 03:43:49 2019 |
Deepak Samuel | How to buy DRS evaluation kit | Dear Stefan,
I have emailed drs4@psi.ch a couple
of times regarding the pricing of the evaluation |
|
747
|
Fri Mar 8 19:35:11 2019 |
Abaz Kryemadhi | ROOT Macro for newest software | The older root macro did not work for me
for data acquired with the newest software.
so for the newest software and |
|
746
|
Wed Mar 6 10:09:01 2019 |
Willy Chang | drscl "no board found" in some Win7 or Win8.X PCs | Hi all,
When connecting the board and running
the Zadig program, some Windows PCs may return "driver |
|
745
|
Mon Feb 25 08:48:27 2019 |
Stefan Ritt | no board found | "dynamic" or "static"
does not matter, as long as you don't
use your program on another computer. I have |
|
744
|
Mon Feb 25 08:40:44 2019 |
Lev Pavlov | no board found |
Hello. When compiling drs_exam,
do you need to use a "static "version |
|
743
|
Thu Feb 21 09:57:53 2019 |
Stefan Ritt | no board found | Could be. Have you tried that elog:657
Stefan
|
|
742
|
Thu Feb 21 09:51:24 2019 |
Lev Pavlov | no board found | Hey. Yes, the program is running as administrator.
By the way, this is win10. Your drs_exam
works fine. My drs_exam compiled wrote no |
|
740
|
Wed Feb 20 12:56:56 2019 |
Stefan Ritt | meg? | No idea. Maye some access problem. Have
you tried to start your program under an
admin account? |
|
739
|
Wed Feb 20 12:13:44 2019 |
Lev Pavlov | meg? | Great, drs_exam compiles without problems.
Now when you run the compiled file drs_exam
writes board not found, but drsosc and drscl |
|
738
|
Wed Feb 20 08:08:42 2019 |
Stefan Ritt | meg? | You have to change the path to libusb-1.0.lib
to the one where you installed it.
Stefan |
|
737
|
Wed Feb 20 08:03:04 2019 |
Lev Pavlov | meg? | Hey. Strange problem. Why does the compiler
refer there at all? Library installed drsosc
works |
|
736
|
Mon Feb 4 18:18:22 2019 |
Stefan Ritt | Different Distances between the sampling points | elog:361
|
|
735
|
Mon Feb 4 17:36:49 2019 |
Hans Steiger | Different Distances between the sampling points | Sorry.... but is there a solution or a
Root Macro, that reads the waveforms into
a Root-Tree? I simply can not work anymore |
|
734
|
Mon Feb 4 16:46:04 2019 |
Stefan Ritt | Different Distances between the sampling points | The sampling points are NOT equidestant,
they have varying bin widths of 150ps to
250ps at 5GS/s. That's due the way the |
|
733
|
Mon Feb 4 16:42:08 2019 |
Hans Steiger | Different Distances between the sampling points | Dear All,
with the older software for my
V5 Board i did not have the problem, that |
|
732
|
Sat Feb 2 10:10:22 2019 |
Stefan Ritt | Saving Rate (only 15Acq/s) | The reduction of rate is because you save
in XML format, which is an ASCII format,
so human readable, but takes long to write. |
|
731
|
Sat Feb 2 00:13:12 2019 |
Hans Steiger | Saving Rate (only 15Acq/s) | Dear All,
when I use my Evaluation Board |
|
730
|
Wed Jan 30 17:08:58 2019 |
Stefan Ritt | ROOT Macro for data acquired with the newest software | This one elog:361
should still work.
Stefan |
|
729
|
Wed Jan 30 08:02:25 2019 |
Stefan Ritt | DRS4 domino wave stability study | The Domino wave is most stable at 5 GSPS,
slowly degrades down to 3-2 GSPS, and at
1GSPS gets some significant jitter. This |
|
728
|
Wed Jan 30 06:51:37 2019 |
Saurabh Neema | DRS4 domino wave stability study | We have been using DRS4 IC in our design
for quite some time and it is giving good
performance. |
|
727
|
Tue Jan 29 14:43:44 2019 |
Abaz Kryemadhi | ROOT Macro for data acquired with the newest software | Hello,
Is there a root macro for decoding
binary data acquired with the newest software |
|
726
|
Thu Nov 8 12:02:34 2018 |
Davide Depaoli | Timing Issue | Thanks a lot for the quick response.
We will do as you suggest.
|
|
725
|
Thu Nov 8 11:54:33 2018 |
Stefan Ritt | Timing Issue | That's not a bug, but a feature of the DRS4
chip. The time bins have different values
by the properties of the chip. They are generated |
|
724
|
Thu Nov 8 11:44:35 2018 |
Davide Depaoli | Timing Issue | Hi,
We are using the DRS4 Evaluation Board as |
|
723
|
Thu Nov 8 09:57:26 2018 |
Stefan Ritt | Pi attenuator on eval board inputs? | The attenuator compensates for the gain
of the buffer which is slightly above one.
In addition, it serves as a "placeholder" |
|
722
|
Mon Nov 5 17:17:08 2018 |
Sean Quinn | Pi attenuator on eval board inputs? | Dear DRS4 team,
I am curious about this part of |
|
721
|
Wed Sep 26 19:21:03 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | In meantime I even updated the manual.
Stefan
|
|
720
|
Wed Sep 26 18:28:20 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I really
appreciate your help.
Thanks! |
|
Draft
|
Wed Sep 26 18:25:07 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I
really appreciate your help.
Thanks! |
|
718
|
Wed Sep 26 14:44:14 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | The "Trigger OUT" has changed
recently. It goes high on a new trigger,
but then STAYS high until the board has been |
|
717
|
Sun Sep 23 02:22:46 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Hello Stefan,
I am using the DRS4 board connected
to a Raspberry PI and through the drsosc |
|
716
|
Thu Sep 13 18:09:13 2018 |
Martin Petriska | "Symmetric spikes" fixed | Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
|
715
|
Tue Sep 4 13:04:30 2018 |
Stefan Ritt | "Symmetric spikes" fixed | Yes it's possible, but I have to find
time for that. The software of the evaluation
board takes care of the spikes ("remove |
|
714
|
Mon Sep 3 11:17:26 2018 |
Martin Petriska | "Symmetric spikes" fixed | Hi,
Is it possible to fix it by FPGA
changes? I see readout cycle (proc_drs_reedout) in |
|
713
|
Tue Aug 21 14:36:44 2018 |
Stefan Ritt | Optimal readout speed | The analog output of the DRS4 chip needs
some time to settle. In principle it need
an infinite amout of time (exponential curve) |
|
712
|
Tue Aug 14 06:10:49 2018 |
Stefan Ritt | Latch delay support | I put that on the wish list, but I won't
have time for that in the next months.
Stefan |
|
711
|
Mon Aug 13 19:44:59 2018 |
Martin Petriska | Latch delay support | Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, |
|
710
|
Wed Aug 1 00:49:30 2018 |
Sean Quinn | Optimal readout speed | Dear DRS4 team,
On page 3 of the data sheet, Table
1. for readout speed a typical value of 10 |
|
709
|
Fri Jul 20 00:44:13 2018 |
Woon-Seng Choong | Effect of interpolation on timing | Just a follow-up update.
It turns out that I was using a
cubic spline interpolation with smoothing. |
|
708
|
Mon Jul 16 19:39:35 2018 |
Woon-Seng Choong | Effect of interpolation on timing | Using a test pulse split into two channels
of the DRS4 Evaluation Board v5, I looked
at the time resolution using a leading edge |
|
707
|
Fri Jun 29 07:51:33 2018 |
Stefan Ritt | Negative Bin Width | Yes that's normal. A negative cell
bin width means that the next cell N+1 samples
the input signal before cell N. This can |
|
706
|
Thu Jun 28 19:55:45 2018 |
Woon-Seng Choong | Negative Bin Width | I am using a DRS4 Evaluation Board v5 and
running the drsosc.exe version 5.06 on
a Window 7 machine. I have performed the |
|
705
|
Tue Jun 19 12:54:51 2018 |
Phan Van Chuan | The data acquisition speed | Thank Stefan Ritt, I added the SoftTrigger()
just after StartDomino(), so now, The data
acquisition speed the same speed as in the |
|
704
|
Tue Jun 19 10:05:50 2018 |
Stefan Ritt | The data acquisition speed | How do you tigger the board? In your code
below you start the board (StartDomino())
and then wait for a trigger. Setting the |
|
703
|
Tue Jun 19 06:42:23 2018 |
Phan Van Chuan | The data acquisition speed | Dear Stefan,
We are using an DRS4 board V5.1
for building a metering system for the scintillator |
|
702
|
Wed Jun 13 16:34:28 2018 |
Julian Kemp | Maximum analog input voltage | Thank you! That solves my problem.
|
|
701
|
Wed Jun 13 13:42:47 2018 |
Stefan Ritt | Maximum analog input voltage | In principle the numbers in the manual
are correct. But they relate to pulses of
a certain length, because the input protection |
|
700
|
Wed Jun 13 13:23:17 2018 |
Julian Kemp | Maximum analog input voltage | Dear all,
I have been wondering what the
maximum analog input voltage for the DRS4 |
|
699
|
Fri Jun 8 08:11:05 2018 |
Stefan Ritt | | Several people reported this problem, but
we cannot reproduce it at our lab. Both the
oscilloscope and the command line interface |
|
698
|
Thu Jun 7 16:27:21 2018 |
Phan Van Chuan | | Dear Stefan,
I am using an DRS4 board to test
the signal from an scintillator detector; |
|
697
|
Thu May 17 13:29:34 2018 |
Stefan Ritt | "Symmetric spikes" fixed | Good news for all DRS4 users. After many
years, I finally understand where the "symmetric
spikes" come from and how to fix them. |
|
696
|
Mon May 14 09:21:29 2018 |
Alessio Berti | WIndows Connection problem with drs507 SOLVED | Hi,
I have a machine with Windows 10
and the solution provided by Steven works |
|
695
|
Wed May 9 14:07:10 2018 |
Alec Shackleford | WIndows Connection problem with drs507 SOLVED | Thank you for this fantastic solution.
I had almost reinstalled windows 7 to see
if that would solve the issue! |
|
694
|
Wed May 9 09:03:52 2018 |
Stefan Ritt | Manual Rev5.1 Figure 1, optional components | I updated the picture in the manual with
a current picture of a Rev5.1 board, and
also added a picture of the bottom side. |
|
693
|
Tue May 8 23:58:35 2018 |
Sean Quinn | Manual Rev5.1 Figure 1, optional components | Dear All,
I'm troubleshooting a board |
|
692
|
Tue May 8 14:43:03 2018 |
Stefan Ritt | Peak at 0 mV in traces | The DRS chip is read out with a 12 bit
ADC, thus the phyical resolution is roughly
1V/4096 = 0.24 mV. I say roughly since the |
|
691
|
Tue May 8 12:15:54 2018 |
Alessio Berti | Peak at 0 mV in traces | Hi Stefan,
following your example, we tried
to perform the same measurement, using drs_exam |
|
690
|
Sun May 6 11:45:09 2018 |
Stefan Ritt | confusion about the description in drs.cpp | The locbus_addr is indeed 32 bits wide,
since the firmware was originally derived
from some firmware running in a VME crate, |
|
689
|
Sun May 6 08:13:37 2018 |
chen wenjun | confusion about the description in drs.cpp | Hi Stefan:
I'm still confused that
althought the 8 bits buffer is enough,the |
|
688
|
Fri May 4 12:11:57 2018 |
Stefan Ritt | Running drs_example.cpp | And here is the second part of your answer:
When you change the input range, you have
to redo the voltage calibration. Best is |
|
687
|
Fri May 4 11:56:08 2018 |
Stefan Ritt | Voltage and Timing Calibration in drs_exam.cpp | Have you set the sampling frequency
b->SetFrequency(5, true);
before the calibration? |
|
686
|
Fri May 4 11:35:20 2018 |
Stefan Ritt | Peak at 0 mV in traces | I tried the following:
- trigger on a 10 MHz sine wave
on CH0, CH1 was open |
|
685
|
Wed May 2 12:23:16 2018 |
Alessio Berti | Peak at 0 mV in traces | Hi,
thank you for the quick reply.
All the bins in the previous histograms have |
|
684
|
Wed May 2 12:12:42 2018 |
Stefan Ritt | Peak at 0 mV in traces | I note that your peak at zero is exactly
twice as high as the bins left and right,
so this looks to me like a binning problem |
|
683
|
Wed May 2 10:44:17 2018 |
Alessio Berti | Peak at 0 mV in traces | Hi,
we modified drs_exam.cpp to read
all 4 channels from the DRS4 and apply directly |
|
682
|
Wed May 2 09:24:53 2018 |
Stefan Ritt | DRS4 using drs_exam.cpp to save as binary files | You have to write the C/C++ code yourself
to write data in binary or any other format.
All information is present after the waveform |
|
681
|
Tue May 1 02:00:40 2018 |
Hyunseong Kim | DRS4 using drs_exam.cpp to save as binary files | Hi,
I would like to save the waveform
in a .dat binary file using drs_exam.cpp. |
|
680
|
Tue Apr 17 13:28:23 2018 |
Stefan Ritt | DRS4 read_binary.cpp | On the software download page at https://www.psi.ch/drs/software-download
you find a link to all versions of the DRS
software, which is located at: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0 |
|
679
|
Mon Apr 16 21:21:29 2018 |
Sobimpe Eniola | DRS4 read_binary.cpp | Hello everyone,
The new read_binary.cpp code
I will be very glad if anyone can |
|
678
|
Fri Apr 13 18:14:07 2018 |
Alessio Berti | Voltage and Timing Calibration in drs_exam.cpp | Hi,
we were trying to implement an
automatic way to calibrate our DRS4 both |
|
677
|
Fri Mar 23 09:39:55 2018 |
Stefan Ritt | Read the CalibrateWaveform | You don't have to read and calibrate
the waveforms in your user code, but can
rely on the DRS.cpp library to do that. Just |
|
676
|
Thu Mar 22 14:36:01 2018 |
Phan Van Chuan | Read the CalibrateWaveform | Helo
I'm building an application for
reading waveforms from the DRS4 board to |
|
675
|
Mon Mar 19 16:22:42 2018 |
Stefan Ritt | ROI | The DRS4 has an internal storage of 1024
capacitors. They work as a ring buffer, so
at 5GSPS you can store 200ns wide signals. |
|
674
|
Mon Mar 19 15:12:02 2018 |
Stefan Ritt | Running drs_example.cpp | The time channel is already calibrated
in ns. So for 5 GSPS, the time scale goes
from zero to 200. Concerning your other issues |
|
673
|
Fri Mar 16 14:00:06 2018 |
Stefan Ritt | confusion about the description in drs.cpp | The FPGA is very small, so it only has
an address space of 256 bytes. Look at the
definition in DRS.cpp |
|
672
|
Thu Mar 15 08:44:26 2018 |
Stefan Ritt | sub-ms precision timestamps? | Putting sub-ms precision into the header
does not make sense, since the USB transfer
only happens in time-slots of about 2 ms. |
|
671
|
Wed Mar 14 09:13:39 2018 |
chen wenjun | confusion about the description in drs.cpp | Hi,Stefan:
recently,whtn I study the
drs.cpp code ,I found that the buffer[1] |
|
668
|
Wed Mar 14 00:38:15 2018 |
Will Flanagan | sub-ms precision timestamps? | Dear DRS4 community,
Is there a way to extract timestamps
with sub-ms precision? The milliseconds of |
|
667
|
Thu Mar 8 22:54:20 2018 |
Rodrigo Trindade de Menezes | Running drs_example.cpp | We found a way to solve the previous problem,
but right now when we try to set the input
range only -0.5 to 0.5 is working. When we |
|
666
|
Wed Mar 7 22:49:38 2018 |
Rodrigo Trindade de Menezes | Running drs_example.cpp | Hello,
We have been using the DRS4 evaluation
board (S/N 2636) that works with the scope |
|
665
|
Fri Mar 2 21:05:48 2018 |
Steven Block | ROI | Great! That is very helpful.
One more question. If no signals
were detected in the 1024*200ps time frame |
|
664
|
Fri Mar 2 20:17:17 2018 |
Stefan Ritt | ROI | N'/N is correct. The 2 us "from
the response you got from me" come from
the fact that after readout, you have to |
|
663
|
Fri Mar 2 18:08:55 2018 |
Steven Block | ROI | Hello,
I have a question about how ROI
works. From what I have read, it will only |
|
662
|
Tue Feb 27 18:12:32 2018 |
Stefan Ritt | DRS4 Dead times | For applications which are critical on
the dead time, one typically uses one ADC
per DRS4 channel, and thus the dead time |
|
661
|
Tue Feb 27 18:04:18 2018 |
Steven Block | DRS4 Dead times | That is extremely helpful! Many thanks.
One more question; If I were to take inputs
from 2 channels at once, would that scale |
|
660
|
Tue Feb 27 17:04:12 2018 |
Stefan Ritt | DRS4 Dead times | XML is very slow to write, and you are
probably limited by that. Switch to binary
mode, which is much faster. You will see |
|
659
|
Tue Feb 27 16:34:26 2018 |
Steven Block | DRS4 Dead times | Hello All,
I am currently trying to figure
out how to properly characterize the dead |
6x |
658
|
Tue Feb 27 13:29:47 2018 |
Stefan Ritt | WIndows Connection problem with drs507 SOLVED | Dear Steven, many thanks for this information,
this is very useful. I know of people having
problems on Windows 10, maybe this will also |
|
657
|
Tue Feb 27 13:17:00 2018 |
Steven Block | WIndows Connection problem with drs507 SOLVED | Hello All,
I too have been struggling with
trying to get the drs4 (507) to work on my |
|
656
|
Thu Jan 25 08:07:32 2018 |
chen wenjun | problem with the drscl(drs507) | I have tried about 4 computers,only one
worked fine.I truly want to know how others
get this fixed,can you get in touch with |
|
655
|
Thu Jan 25 08:00:16 2018 |
Stefan Ritt | problem with the drscl(drs507) | This problem has been reported by several
people, like elog:551
So far I could not solve it. On |
|
654
|
Thu Jan 25 06:10:52 2018 |
chen wenjun | drscl doesn't find eval board but drsosc does (Windows 7) | Hi! Jim:
It seems that I meet the
same question with you ,and I am confused |
|
653
|
Thu Jan 25 05:24:05 2018 |
chen wenjun | problem with the drscl(drs507) | Hi! Stefan:
when I change a new computer(win7,64bit),I
meet a problem that the drscl app cannot |
|
652
|
Wed Jan 17 10:09:09 2018 |
Stefan Ritt | The input signals recorded are different with the signal showed in oscilloscope | First thing is to do another voltage calibration.
Disconnect input, "Config", "Execute
Voltage Calibration". If this does not |
|
651
|
Wed Jan 17 09:51:16 2018 |
Tran Cong Thien | The input signals recorded are different with the signal showed in oscilloscope | Dear Stefan,
I am using an DRS4 board to record
the signals from an plastic scintillator |
|
650
|
Wed Dec 20 22:14:35 2017 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp | https://bitbucket.org/ritt/drs4eb
|
|
649
|
Wed Dec 20 16:30:45 2017 |
Yoni Sher | cascading -- DRS4 Osci.cpp & DRS.cpp | Hi,
The board is modified (and checks
out with the DRSScope program). Could you |
|
648
|
Wed Dec 20 16:21:42 2017 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp | First you need a board which is modified
in hardware to support channel cascading.
Basically there are internal resistors which |
|
647
|
Wed Dec 20 15:30:38 2017 |
Yoni Sher | cascading -- DRS4 Osci.cpp & DRS.cpp | Hi,
I'm trying to do the same thing
(get 1 channel with 8192 bins), but I'm |
|
646
|
Tue Dec 12 13:58:06 2017 |
Stefan Ritt | External trigger using Raspberry Pi | Indeed the code does not work for the current
evaluation board, it has been written for
a previous version and never been updated. |
|
645
|
Tue Dec 12 00:25:50 2017 |
Diego Yankelevich | External trigger using Raspberry Pi | Dear Steffan:
We have been able to use the
DRS4 using a Raspberry Pi but we have not |
|
644
|
Wed Nov 22 14:52:31 2017 |
Stefan Ritt | Averaging capabilities | This feature is not yet implemented. The
(disabled) software swtich is more like a
kind of a reminder to myself to work on that |
|
643
|
Wed Nov 22 09:19:11 2017 |
chen wenjun | using of the DRS Command Line Interface | Thank you very much !! All my fault for
I thought it too comlicated. Thank you sincerely!
|
|
642
|
Wed Nov 22 09:14:18 2017 |
Stefan Ritt | using of the DRS Command Line Interface | Remove the check mark from the "Lock"
box and enter a different value in the sampling
speed box and hit return. |
|
641
|
Wed Nov 22 08:58:33 2017 |
chen wenjun | using of the DRS Command Line Interface | OK!Thank you! One more question,when I
use the Oscillocope ,I found that the actual
speed is a constant value of 1.007G,how can |
|
640
|
Wed Nov 22 08:48:36 2017 |
Stefan Ritt | using of the DRS Command Line Interface | The command line interface is more a debugging
tool for experts, and you are not supposed
to use it except to test the connection to |
|
639
|
Wed Nov 22 08:31:03 2017 |
chen wenjun | using of the DRS Command Line Interface | Hello! I'm using DRS4 evaluation board
V5 with the drs command line interface,but
the mannal only explained the meaning of |
|
638
|
Thu Nov 16 02:55:44 2017 |
Diego Yankelevich | Averaging capabilities | The Display window in the Oscilloscope
software shows averaging capabilites but
I have not been able to activate these. Is |
|
637
|
Fri Nov 3 13:28:04 2017 |
Stefan Ritt | Triggering using AND | Think about: How would you make a coincidence
(AND) between two edges? Since an edge is
infinitesimally small, there is no way to |
|
636
|
Fri Nov 3 12:11:14 2017 |
Håkan Wennlöf | Triggering using AND | Hi!
I'm using the DRSOsc program,
and I have a question that I need a bit clarified; |
|
635
|
Wed Oct 18 11:48:14 2017 |
Vadym Denysenko | Time offset | Thank you for your reply!
|
|
634
|
Wed Oct 18 09:12:26 2017 |
Stefan Ritt | Time offset | No this is not possible. But you can delay
your signal externally (like with a delay
cable or electronically) and then send the |
|
633
|
Tue Oct 17 14:58:58 2017 |
Vadym Denysenko | Time offset | Hello.
I have a simple question, can I |
|
632
|
Mon Oct 16 15:35:22 2017 |
Stefan Ritt | Raspberry Pi Connection Failure | Have you tried as root? Maybe you miss
some permissions.
Stefan |
|
631
|
Fri Oct 13 03:39:01 2017 |
Jonathan Wapman | Raspberry Pi Connection Failure | I am currently attempting to use a raspberry
pi to connect to the DRS 4 board. I whenever
I try to use the DRS Command Line TOol, Revision |
|
630
|
Mon Oct 2 16:08:05 2017 |
Stefan Ritt | Event acquisition pace for irregular timing | As written in the documentation, the DRS
evaluaiton board has a maximum trigger capability
of ~500 Hz. This is limited by the USB bus |
|
629
|
Wed Sep 27 16:11:03 2017 |
Yoni Sher | Event acquisition pace for irregular timing | Hi,
I'm running a LIDAR application
that requires that every outgoing pulse be |
|
628
|
Sun Aug 27 12:44:16 2017 |
Yuvaraj Elangovan | DRS4 version Support | Hi i am using DRS4 Eval Board V2, How to
acquire data to a bin file using it.
|
|
627
|
Tue Jul 25 14:47:05 2017 |
Volodymyr Rodin | Time output | Hi again.
Okay, it works with 5.05 version very
good and it is enough for me. |
|
626
|
Fri Jul 21 09:16:02 2017 |
Volodymyr Rodin | Time output | Hello Stefan
I tried to convert binary to a
simple txt file and found next problem - |
|
625
|
Thu Jul 20 13:00:44 2017 |
Volodymyr Rodin | Driver installation on Windows 10 | Dear Laura
You need to disable driver signature
enforcement. Then try again with path |
|
624
|
Wed Jul 12 20:16:05 2017 |
Stefan Ritt | Time resolution between boards | Yes this should be possible.
Stefan
|
|
623
|
Wed Jul 12 04:24:39 2017 |
Toshihiro Nonaka | Time resolution between boards | Hello,
I 'm using four evaluation
boards v.3 to construct the multi-board DAQ |
|
622
|
Fri Jul 7 10:31:47 2017 |
Stefan Ritt | Trigger setting (AND AND) OR (AND AND) | Unfortunately not with the current firmware.
Stefan
|
|
621
|
Thu Jul 6 15:10:48 2017 |
Esperienza Giove | Trigger setting (AND AND) OR (AND AND) | Hello there,
is it possible to setup trigger
in double AND configuration (a pair in and |
|
620
|
Thu Jun 22 21:36:08 2017 |
Stefan Ritt | AND Trigger problems with 2-3 channels | Hi,
from our screenshots I see the
following: |
|
619
|
Fri Jun 16 17:34:20 2017 |
Laura Gonella | Driver installation on Windows 10 | Hello,
I am trying to get a DRS4 board
to run on Windows 10. I am having problems |
|
618
|
Fri Jun 9 09:44:33 2017 |
Rebecca Schmitz | AND Trigger problems with 2-3 channels | Hello,
It
seems that a coincidence with two fixed channels |
|
617
|
Thu Jun 8 15:52:20 2017 |
Stefan Ritt | AND Trigger problems with 2-3 channels | Can you post a screenshot where I can see
the channel waveforms, the configuration
and the trigger settings? |
|
616
|
Thu Jun 8 14:26:23 2017 |
Rebecca Schmitz | AND Trigger problems with 2-3 channels | Hello,
I work with the DRS4 Evaluation
Board V5 and I have a problem with the software. |
|
615
|
Tue May 30 21:22:10 2017 |
Esperienza Giove | Setting input range | Thank you
|
|
614
|
Tue May 30 21:00:26 2017 |
Stefan Ritt | Setting input range | See elog:531
|
|
613
|
Tue May 30 20:45:30 2017 |
Esperienza Giove | Setting input range | Hello,
is it possible to set a completely
negative input range like -1 to 0 or -0.95 |
|
612
|
Fri May 26 08:48:25 2017 |
Stefan Ritt | Invalid magic number 0000 | There is no other way to reset the board.
As I said, people running this under Windows
or MacOS are fine, so maybe this calls for |
|
611
|
Thu May 25 20:20:57 2017 |
Esperienza Giove | Invalid magic number 0000 | Hello, thanks for your answer. Unluckily
if i try to reset in this way it keeps hanging
musb_write: requested |
|
610
|
Thu May 25 20:17:41 2017 |
Esperienza Giove | Invalid magic number 0000 | Hello, thanks for your answer. Unluckily
if i try to reset in this way it keeps hanging
musb_write: requested |
|
609
|
Tue May 23 10:24:47 2017 |
Stefan Ritt | Invalid magic number 0000 | Under linux, many people observed that
the USB connection is unstable to the evaluation
board. This must be related to the linux |
|
608
|
Mon May 22 18:27:56 2017 |
Esperienza Giove | Invalid magic number 0000 | Hello everybody!
After some times i init my board,
or if i stop the program during the acquisition, |
|
607
|
Thu Apr 20 06:30:13 2017 |
Strahinja Lukic | Wave rotation during transfer from the board? | Thanks.
Strahinja
|
|
606
|
Wed Apr 19 12:17:25 2017 |
Stefan Ritt | Wave rotation during transfer from the board? | This is correct. Actually the amplitude
array is rotated already inside the DRS4
chip. So the readout starts with the stop |
|
605
|
Sat Apr 15 03:48:31 2017 |
Strahinja Lukic | Wave rotation during transfer from the board? | I don't know if this question is already
documented elsewhere.
I am developing a DAQ code for |
|
604
|
Thu Apr 13 17:10:58 2017 |
Christian Farina | Stand-alone Time Calibration for PSI Board | Thank you for your help Stefan. I will
try to get the TC part isolated.
|
|
603
|
Thu Apr 13 17:02:01 2017 |
Stefan Ritt | Stand-alone Time Calibration for PSI Board | Than you can try to isolate the code. Note
that different SCAs might work differently.
Like the DRS4 has a channel-to-channel jitter |
|
602
|
Thu Apr 13 16:54:32 2017 |
Christian Farina | Stand-alone Time Calibration for PSI Board | Hi Stefan,
Thank you for your reply. I have
read the paper already. I looked through |
|
601
|
Thu Apr 13 16:50:18 2017 |
Stefan Ritt | Stand-alone Time Calibration for PSI Board | Hard to say. Timing calibration is quite
delicate. If you start from scratch, better
read this paper: https://arxiv.org/abs/1405.4975 |
|
600
|
Thu Apr 13 16:42:21 2017 |
Christian Farina | Stand-alone Time Calibration for PSI Board | Hello everybody,
I was trying to create a stand-alone
program that would perform a time calibration |
|
599
|
Tue Apr 11 09:41:44 2017 |
Stefan Ritt | drs4 registers behaviour | What I do is the following: Have the RESET
input unconnected. When you power up, this
makes an internal reset during the power |
|
598
|
Tue Apr 11 09:07:33 2017 |
Giovanni Bruni | drs4 registers behaviour | Thank you Stefan for replying!
I have still the RESET issue in mind:
how would you suggest to reset properly the |
|
597
|
Mon Apr 10 14:05:17 2017 |
Stefan Ritt | drs4 registers behaviour | 1. WRITE SHIFT register and CONFIG registers
are initialized to "1" on power
up, but if you want to change that, use A0-A3 |
|
596
|
Mon Apr 10 13:41:41 2017 |
Giovanni Bruni | drs4 registers behaviour | Hej Stefan! Thank you for your answer!
Just to be sure to have understood
properly: |
|
595
|
Mon Apr 10 10:50:57 2017 |
Stefan Ritt | drs4 registers behaviour | Using the RESET line to reset registers
is not a good idea since it can have some
bad side-effects. The READ SHIFT register |
|
594
|
Mon Apr 10 10:48:03 2017 |
Stefan Ritt | DRS4 eval board v4 coincidence firmware changes for triger for short pulses | You have to download the package for your
board, which then includes also the correct
firmware for your board. If you have a V4 |
|
593
|
Mon Apr 10 08:50:11 2017 |
Giovanni Bruni | drs4 registers behaviour | Hej everyone!
I have some questions regarding what
happens to some DRS registers in some scenarios: |
|
592
|
Wed Apr 5 12:40:16 2017 |
Martin Petriska | DRS4 eval board v4 coincidence firmware changes for triger for short pulses | I would like to implement fpga firmware
changes for DRS4 eval board v4 to put there
posibility for standard coincidence (for |
|
591
|
Wed Apr 5 12:28:28 2017 |
Stefan Ritt | drscl doesn't find eval board but drsosc does (Windows 7) | Two people report now this problem, while
this works fine at our lab. So I'm puzzled
right now. |
|
590
|
Tue Mar 28 21:53:12 2017 |
Jim Freeman | drscl doesn't find eval board but drsosc does (Windows 7) | I cannot find the EVAL board using drscl
version 5.06 while the drsosc works fine.
I tried 2 different eval boards and 2 different |
|
589
|
Fri Feb 24 18:35:38 2017 |
Stefan Ritt | Passing parameters to drscl | This is indeed currently not implemented.
But there is a simple C program drs_exam.cpp,
which connects to a board and safes some |
|
588
|
Fri Feb 24 17:34:28 2017 |
Tarik Zengin | Passing parameters to drscl | Hi everyone,
I wonder if there is a way to pass
parameters to drscl. What I specifically |
|
587
|
Tue Jan 31 08:40:04 2017 |
Stefan Ritt | LLD and ULD discriminations, | Not inside the board. Each channel has
a single discriminator. You can select to
trigger on a rising or falling edge, but |
|
586
|
Tue Jan 31 01:37:35 2017 |
VO HONG HAI | LLD and ULD discriminations, | Dear Stefan,
Is there any way to develop
LLD and ULD discrimination in DSR-4 evaluation
board?
Best regards,
V.H.Hai |
|
585
|
Mon Jan 30 16:37:33 2017 |
Stefan Ritt | AND trigger problems | In the evaluation board we use an ADCMP601
comparator, which has a setup and hold time
of 4.6 ns. So a pulse which exceeds the threshold |
|
584
|
Sat Jan 28 14:11:58 2017 |
Danny Petschke | AND trigger problems | Dear Stefan,
I have 2 identical pulses as a
splittet signal with an amplitude of 300mV. |
|
583
|
Fri Jan 13 13:50:10 2017 |
Stefan Ritt | DRS software doesn't work under Windows XP SP3 | Can you try that executable under XP: https://www.dropbox.com/s/j1n09afhbmh0zzu/drsosc.exe?dl=0
|
|
582
|
Fri Jan 13 13:16:09 2017 |
Stefan Ritt | DRS software doesn't work under Windows XP SP3 | The error probably comes from the fact
that the drsosc.exe application is a 64-bit
application and cannot be executed under |
|
581
|
Fri Jan 13 12:58:22 2017 |
Gregor Kramberger | DRS software doesn't work under Windows XP SP3 | Hi all
I have a problem with running the
DRSOSC under windows XP SP3. We have some |
|
580
|
Fri Dec 9 04:17:46 2016 |
Abhishek Rajput | Potential Incorrect Timing Calibration for DRS4 Data | Hello Stefan,
Many thanks for the explanations.
You've cleared my confusion in this matter. |
|
579
|
Fri Dec 2 16:47:37 2016 |
Stefan Ritt | DRS4 Initiation | No, I can't think of anything else.
There is no intermediate addressing stage.
The only thing which sometimes happens is |
|
578
|
Fri Dec 2 15:32:52 2016 |
samridha kunwar | DRS4 Initiation | Thanks for replying Stefan.
I was more so just concerned with
the steps in the firmware when I had asked. |
|
577
|
Wed Nov 30 19:05:24 2016 |
Stefan Ritt | DRS4 Initiation | Uhh, there are 1000 things which might
be wrong. A bit like "my car is not
working, it makes strange noise". Without |
|
576
|
Wed Nov 30 17:48:39 2016 |
samridha kunwar | DRS4 Initiation | I am having a general problem getting read
back using the ROI mode. In the transparent
mode everything looks good. These are the |
|
575
|
Wed Nov 30 10:45:29 2016 |
Stefan Ritt | Long timing between two channels | You cannot measure times longer than 1024/sampling
rate.
Stefan |
|
574
|
Wed Nov 30 08:53:58 2016 |
Stefan Ritt | Potential Incorrect Timing Calibration for DRS4 Data | The inverter chain in the DRS4 is continously
running in a ring. Once you get a trigger,
it is stopped. This happens in any of the |
|
573
|
Tue Nov 29 23:19:06 2016 |
Abhishek Rajput | Potential Incorrect Timing Calibration for DRS4 Data | Hello Stefan,
Thank you for the excellent explanation
and diagram. This part of the code is now |
|
572
|
Mon Nov 28 22:28:34 2016 |
Randall Gladen | Long timing between two channels | I don't believe I fully understand
how the timing works between multiple channels
on DRS4 board, even after reading the manual, |
|
571
|
Mon Nov 28 16:52:38 2016 |
Stefan Ritt | PLL did not lock | Have you tried to unplug and re-plug the
board a few times? According to our database,
you should have three boards. Do all three |
|
570
|
Mon Nov 28 16:48:15 2016 |
Alexey Lubinets | PLL did not lock | The serial number is 2586. This board is
about two years old, and it might be in use
(but I do not know exactly). |
|
569
|
Thu Nov 24 13:24:26 2016 |
Stefan Ritt | Potential Incorrect Timing Calibration for DRS4 Data | The code in the macro is correct. The misconception
lies in the definition what "sample
0" means. Please view the attached picture. |
|
568
|
Thu Nov 24 08:13:23 2016 |
Stefan Ritt | PLL did not lock | Which serial number has the board? Has
it been in use before or is it a new board?
Stefan |
|
567
|
Thu Nov 24 00:40:38 2016 |
Alexey Lubinets | PLL did not lock | Hello, everybody!
I installed DRSosc and DRScl. Command
line works normally (at least, it can "see" |
|
566
|
Wed Nov 23 08:17:23 2016 |
Abhishek Rajput | Potential Incorrect Timing Calibration for DRS4 Data | Hello,
I was running through a particular
binary file containing data taken on all |
|
565
|
Mon Nov 21 14:13:32 2016 |
Stefan Ritt | Channel offsets in GetTime() | Cell 700 is arbitrary. You can choose any
cell to align the channels to each other.
The only requirement is that it's always |
|
564
|
Fri Nov 18 16:38:42 2016 |
Gerard Montarou | LabView | Hello,
Did you start to write some VI
to interface DRS4board with labview ? |
|
563
|
Fri Nov 18 05:52:45 2016 |
Kurtis Nishimura | Channel offsets in GetTime() | Hello,
I have a question about the GetTime()
method in DRS.cpp. I understand how |
|
562
|
Thu Nov 10 22:07:40 2016 |
Stefan Ritt | Break Statements in DRS4 Binary to ROOT Macro | You're right, fread() return the number
of objects read, so indeed it should be one
if successful. |
|
561
|
Thu Nov 10 20:54:45 2016 |
Christian Farina | Missing Header | Hi Stefan,
I have already read the paper.
I was just unsure where the calibration code |
|
560
|
Thu Nov 10 19:24:52 2016 |
Abhishek Rajput | Break Statements in DRS4 Binary to ROOT Macro | Hello,
I am wondering why the code should
be changed to i < sizeof(eh), since doesn't |
|
558
|
Thu Nov 10 09:56:04 2016 |
Stefan Ritt | Break Statements in DRS4 Binary to ROOT Macro | Hi,
fread() returns the number of bytes
read and zero (I believe) if there is an |
|
557
|
Thu Nov 10 04:41:24 2016 |
Abhishek Rajput | Break Statements in DRS4 Binary to ROOT Macro | Hello,
I recently modified the binary
to ROOT convertor written by Stefan (https://midas.psi.ch/elogs/DRS4+Forum/361) |
|
556
|
Wed Nov 9 19:49:07 2016 |
Stefan Ritt | Missing Header | Best is to read this paper: https://arxiv.org/abs/1405.4975
The source code for that is in
DRS.cpp in the DRS software distribution |
|
555
|
Wed Nov 9 17:19:48 2016 |
Christian Farina | Missing Header | Thank you Stefan, that was just what I
needed.
Also, I have another question, |
|
554
|
Tue Nov 8 10:20:52 2016 |
Stefan Ritt | Missing Header | The web page from where you downloaded
the software contains a sentence "requires
libusb-1.0 package". Please install |
|
553
|
Fri Nov 4 17:41:03 2016 |
Christian Farina | Missing Header | Hello everybody,
I am completely new to this, so
please bear with me. |
|
552
|
Fri Oct 28 15:51:59 2016 |
Stefan Ritt | Problems with DRS command line | No, I absolutely have no idea. Both DRSOsc
and drscl use exaclty the same code to access
USB.
|
|
551
|
Fri Oct 28 15:02:18 2016 |
Simon Mendisch | Problems with DRS command line | [quote="Stefan Ritt"]
You are the first one describing this problem
(out of ~200 people), so I guess the problem |
|
550
|
Thu Oct 27 08:29:26 2016 |
Stefan Ritt | Problems with DRS command line | [quote="Alexey Lubinets"]Hello, everybody
I have installed the software for the DRS4 |
|
549
|
Wed Oct 26 21:15:35 2016 |
Alexey Lubinets | Problems with DRS command line | Hello, everybody
I have installed the software for the DRS4 |
|
548
|
Tue Oct 11 22:11:26 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks |
|
547
|
Tue Oct 11 09:20:04 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Concerning the offset, it looks to me like
you moved the offset slider slider of channel
1 to a non-zero position. You see that from |
|
546
|
Tue Oct 11 09:04:33 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
thanks for the paper. That makes
sense. I thought about sth. like that but |
|
545
|
Mon Oct 10 12:03:27 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Ok, I got it. The timing resolution is
affected by the signal-to-noise ratio over
the rise-time of your signal. You find the |
|
544
|
Mon Oct 10 11:30:37 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
Chn2 & Chn3 were used for delay-determination as
you can see on the second picture. |
|
543
|
Sun Oct 9 11:39:18 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Can you post a screenshot of your measurement?
Stefan
|
|
542
|
Sun Oct 9 10:43:35 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | (Board Type:9, DRS4)
Hello,
I´m trying to reach the timig |
|
541
|
Thu Oct 6 15:23:18 2016 |
Will Flanagan | | Hi Stefan,
That is exactly what I'm looking
for. Thanks again! |
|
540
|
Thu Oct 6 11:18:05 2016 |
Stefan Ritt | Timestamp for each DRS4 waveform | In the mentioned read_binary.cpp file you
have the line where you read the event header
i = fread(&eh, sizeof(eh), |
|
539
|
Wed Oct 5 22:43:29 2016 |
Will Flanagan | Timestamp for each DRS4 waveform | Hi DRS4 Experts,
I have been analyzing DRS4 binary
data with scripts based on Stefan's (very |
|
538
|
Fri Sep 30 17:03:38 2016 |
Stefan Ritt | Output Timing Drifting | Hi Jacob,
you are missing the timing calibration.
Each sampling cell has not the same width. |
|
537
|
Thu Sep 29 17:26:13 2016 |
Jacob Hwang | Output Timing Drifting | Hello,
I have designed four DRS4 chips
(36 channels) on my board running at 1GHz |
|
536
|
Mon Aug 29 12:51:48 2016 |
Stefan Ritt | increment write config register on the fly? | The problem is when you change the write
config register from 11111111 to 01111111,
or from 00001111 to 00000111, then the last |
|
535
|
Mon Aug 29 12:18:49 2016 |
benjamin legeyt | increment write config register on the fly? | If I may trouble you for a little more
information, the critical point then is
that there should not be any zeroes in the |
|
534
|
Mon Aug 29 10:57:33 2016 |
Stefan Ritt | increment write config register on the fly? | The issue with "stopping at cell 767"
would also affect this mode of operation.
Furthermore, the DRS4 chip has only 10 bit |
|
533
|
Mon Aug 29 09:36:34 2016 |
benjamin legeyt | increment write config register on the fly? | Hello,
I have a question about using the
write config register to enable/disable sampling |
|
531
|
Wed Jun 29 09:10:01 2016 |
Stefan Ritt | Negative input signals | Hello everybody,
I get often asked if the DRS4 evaluation
board can accomodate negative input pulses |
|
530
|
Wed Jun 15 14:49:00 2016 |
Stefan Ritt | problems of DRS4 | 1. Simultaneous writing and reading is
not possible with the DRS4 chip. The manual
says differently on p. 14, but due to a bug |
|
Draft
|
Sun Jun 12 08:49:54 2016 |
Michael | problems of DRS4 | Hi
I want to use DRS4 to
digitize 16 channels of signals. The width |
|
528
|
Sun Jun 12 08:45:52 2016 |
Michael | problems of DRS4 | Hi
I want to use DRS4 to
digitize 16 channels of signals. The width |
|
527
|
Wed Jun 1 23:16:01 2016 |
Stefan Ritt | problems when stop cell >= 767 ?? | I cannot confirm the story with the "stop
capacitor > 767". It can be seen
from your plots that the distribution of |
|
526
|
Wed Jun 1 22:29:01 2016 |
Dominik Neise | problems when stop cell >= 767 ?? | Hello Stefan,
some colleages told me a story,
I was neither able to confirm nor find anything |
|
525
|
Thu May 12 12:38:17 2016 |
Stefan Ritt | DRS4 Macro to save events | Dear Maksat,
If your car does not run, and you
call the car dealer and tell him "my |
|
524
|
Thu May 12 08:16:41 2016 |
Stefan Ritt | Problem For Software Download | Can you tell me (screendump) what is the
problem on the web site https://www.psi.ch/drs/software-download ?
It should redirect you to |
|
523
|
Thu May 12 05:18:47 2016 |
Yu | Problem For Software Download | Hi
I can't download the
software for windows on this website 'www.psi.ch/drs/software-download', |
|
522
|
Wed May 11 15:48:57 2016 |
SANDJONG Saturnin Orly | Probléme de Calibration de la DRS4 | Bonjour, Je suis en stage dans un laboratoire
ou on utilise pour echantillonnage des données,
une cartes DRS4 5GSPS avec 1024 cell, mon |
|
521
|
Wed May 11 04:01:14 2016 |
Maksat | DRS4 Macro to save events | Dear Stefan,
I am trying to setup DRS inside
radiation enclosure and would like to write |
|
520
|
Mon May 2 14:31:28 2016 |
Dmitry Hits | two DRS4 boards configuration with 2048 samples each | Hi Stefan
Any chance you have time to fix
the software for multiboard configuration |
|
519
|
Thu Apr 28 15:47:53 2016 |
Stefan Ritt | New software version and binary format | A new software version 5.0.5 has been released
today. This fixes a few bugs in multi-board
configurations, and adds saving of the scaler |
|
518
|
Thu Apr 28 15:46:34 2016 |
Stefan Ritt | Best settings for time measurements | The DRS4 chip has been designed to work
best at high sampling speeds. At 700 MSPS,
the chip is at it's limit and timing |
|
517
|
Wed Apr 27 20:04:12 2016 |
Abaz Kryemadhi | Best settings for time measurements | I am studing some pulses that are about
200-300 ns wide and a rise time of few ns,
which settings would be best for coincidence |
|
516
|
Wed Apr 27 09:51:37 2016 |
Toshihiro Nonaka | serial number problem | The serial number has been fixed by
using drscl. Thank you!
|
|
515
|
Wed Apr 27 09:04:01 2016 |
Stefan Ritt | serial number problem | If dis- and reconnecting the board does
not help, there is the (small) chance that
the serial number got erased in the board. |
|
514
|
Wed Apr 27 08:14:14 2016 |
Toshihiro Nonaka | serial number problem | Dear all,
I'm using 3 DRS boards simultaneously
and their serial numbers are 2169, 2170, |
|
513
|
Tue Apr 26 13:42:42 2016 |
Stefan Ritt | DRS4 purchase information | Just be patient. Anita is not at work this
week.
|
|
512
|
Tue Apr 26 09:54:16 2016 |
Stefan Ritt | Negative fCellDT values from GetTimeCalibration() | I just realized that the negative bin widht
is not explicitly mentioned in the quoted
paper. So let me explain it here: |
|
511
|
Sat Apr 23 12:33:17 2016 |
Daniel Stricker-Shaver | Negative fCellDT values from GetTimeCalibration() | Hi Kyle,
If I remember right the negative
sampling width happens only for 498 and at |
|
509
|
Thu Apr 21 22:16:43 2016 |
Kyle Weinfurther | Negative fCellDT values from GetTimeCalibration() | Hello Stefan,
I am using four DRS4 v5 eval boards
to digitize 16 channels of data. I have recently |
|
508
|
Fri Apr 15 12:58:46 2016 |
Konstantin Gusev | DRS4 purchase information | Hi,
I can't contact with
Anita Van Loon about DSR4 chip's price |
|
507
|
Wed Apr 6 09:46:10 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run |
Martin Petriska |
|
506
|
Wed Apr 6 09:43:52 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run | At hight rates I worked with files of up
to 20 GB so I don't think this is the
problem. |
|
505
|
Wed Apr 6 09:01:28 2016 |
Martin Petriska | DRS Oscilloscope freezing after a long run |
|
|
504
|
Wed Apr 6 08:41:08 2016 |
Stefan Ritt | DRS Oscilloscope freezing after a long run | Even with writing for one night no problem
(see below). Have you checked how big your
data file is? I guess there is a limit under |
|
503
|
Tue Apr 5 16:08:59 2016 |
Stefan Ritt | DRS Oscilloscope freezing after a long run | I tried this night to run the board at
a 10 Hz rate with an external pulser, without
writing, and it did not freeze after ~14 |
|
502
|
Mon Apr 4 12:08:15 2016 |
Stefan Ritt | DRS Oscilloscope freezing after a long run | Then it seems that there is some USB communication
problem. I heard this also from other people,
that the USB data transfer under Windows |
|
501
|
Mon Apr 4 11:41:26 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run | Dear Stefan Ritt,
Yes I use Windows 7, If the DRS
Oscilloscope program stays |
|
500
|
Mon Apr 4 11:31:34 2016 |
Stefan Ritt | DRS Oscilloscope freezing after a long run | Dear Daniel,
sorry my late reply, I'm pretty
busy these days. The behavior you report |
|
499
|
Sun Apr 3 22:34:28 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Thanks, great!
|
|
498
|
Sun Apr 3 22:10:19 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | No there are no other components. I put
a photo of the inverter with its cables SMA
and one end, BNC at the other. You can see |
|
497
|
Sat Apr 2 17:22:34 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Thanks again, this is very
useful, just another question did you
put any other passive elements in the circuit |
|
496
|
Sat Apr 2 11:41:07 2016 |
Stefan Ritt | Question about timimng calibration | The evaluation board normally has 1024
bins per channel. We offer an option with
2048 bins using channel cascading, to capture |
|
495
|
Sat Apr 2 11:21:10 2016 |
Felix Bachmair | Question about timimng calibration | Hi,
I am trying to understand some
details about the timing calibration. |
|
494
|
Fri Apr 1 22:09:07 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | The coilcraft part number is: JA4220-ALB.
Iordered two of them and they were sent as
free samples. You might want to buy some |
|
493
|
Fri Apr 1 01:30:40 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Hi Chris,
I am looking at Sensl SiPMs
as well, can you send the part number |
|
492
|
Thu Mar 31 20:48:00 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | I needed a fast pulse inverter in order
to feed signals from the recent SensL SiPMs
into a conventional CFD which only accepted |
|
491
|
Thu Mar 31 20:38:05 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Thanks, that looks just fine.
|
|
490
|
Thu Mar 31 20:34:25 2016 |
Stefan Ritt | Trigger on the And of a positive and negative signal | Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups
|
|
489
|
Thu Mar 31 19:44:38 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Ok, thanks! do you know an easy in-line
inverter like mini-circuit or digikey?
Can also redesign the detector I gues to |
|
488
|
Thu Mar 31 19:35:06 2016 |
Stefan Ritt | Trigger on the And of a positive and negative signal | No. You have to use an inverter for one
of your signals.
Stefan |
|
487
|
Thu Mar 31 19:30:26 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | I would like to be able to trigger in this
fashon: channel 0 > 0.1 and. channel
1< -0.1, because I have a positive |
|
486
|
Tue Mar 22 12:54:41 2016 |
Stefan Ritt | | Yes this is correct. But it is a sample-and-hold
circuit. So the sampling cell follows the
input for 3.2 ns, then samples and holds |
|
485
|
Mon Mar 21 10:38:27 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run | Dear Stefan Ritt,
I am using a DRS4 v5 to do timing
measurements of Positron lifetime. I use |
|
484
|
Fri Mar 11 19:50:18 2016 |
Dominik Neise | | Hello Stefan,
I just stumbled again over a phrase
in the DRS4 datasheet I never really understood, |
|
483
|
Wed Mar 9 09:57:20 2016 |
Christian D | LabView | Hi,
I would like to use the DRS4 board
with LabView for fast readout. |
|
482
|
Mon Feb 29 14:09:21 2016 |
Stefan Ritt | two DRS4 boards configuration with 2048 samples each | The multi-board mode has never been tested with
2048 samples, so is very likely not to work.
I don't know yet how much work this will |
|
481
|
Mon Feb 29 13:33:06 2016 |
Dmitry Hits | two DRS4 boards configuration with 2048 samples each | Dear Stefan,
I daisy-chained two boards (master
sn#: 2514 - slave sn#: 2513) each with 2048 |
|
480
|
Mon Feb 29 13:09:29 2016 |
Stefan Ritt | baseline shift | The baseline shift comes from some instable
power supply inside the evaluation board
which cannot be controlled to the mV level. |
|
479
|
Mon Feb 29 12:58:17 2016 |
Dmitry Philippov | baseline shift | Hello! My name is Dmitry. I am from SiPM
Lab is NRNU MEPhI (Russia, Moscow). We bought
DRS4 evaluation board V5 with firmware 21305. |
|
478
|
Tue Feb 16 11:55:54 2016 |
Martin Petriska | Saving histogram data |
|
|
477
|
Tue Feb 16 11:21:43 2016 |
Stefan Ritt | Saving histogram data | There is no histogram save functoinality
in ther DRSOscilloscope program - on purpose.
The board and the software are meant to evaluate |
|
476
|
Fri Jan 15 08:09:00 2016 |
Stefan Ritt | Triggering of DRS4 in the fastest sampling mode | Hi Chris,
if you ever used an oscilloscope,
you might be familar with the button controlling |
|
475
|
Thu Jan 14 21:49:37 2016 |
Chris Thompson | Triggering of DRS4 in the fastest sampling mode | I am attempting to use the DRS4 to measure
the timing resolution of a pair of SensL
silicon photomultipliers (SiPM). In order |
|
474
|
Thu Jan 14 14:11:06 2016 |
Stefan Ritt | Dtap stops toggling after 40msec | Thanks for the update, I will add a note
into the data sheet.
|
|
473
|
Thu Jan 14 14:00:26 2016 |
mony orbach | Dtap stops toggling after 40msec | surrey i forgot to update..
after carefully examining our VHDL
we found out that there are brief times that |
|
472
|
Tue Jan 12 21:02:31 2016 |
Stefan Ritt | Compiling DRS-exam | I guess you are compiling under MS Windows
??? You probably don't link correctly
to the USB lib. Try to compile the examples |
|
471
|
Tue Jan 12 17:57:03 2016 |
Jack Bargemann | Compiling DRS-exam | I am trying to compile drs-exam, but am
getting an error message I do not understand:
1>musbstd.obj |
|
470
|
Tue Jan 12 16:06:07 2016 |
Stefan Ritt | Use of Channel Cascading in drs_exam.cpp | Hi Larry,
sorry my late reply, swamped with
work here. You were right in the modifictions |
|
469
|
Tue Jan 12 15:42:31 2016 |
Larry Byars | Use of Channel Cascading in drs_exam.cpp | An update. I have been successful in making
modifications to drs_exam.cpp so that I can
get 2048 samples per channel.. The main changes |
|
468
|
Tue Jan 12 12:57:46 2016 |
Stefan Ritt | PC software beyond Windows 7 | The 5.0.4 version was corrupt on our server.
I fixed it, so now it shoudl also work fine
(although there are only very minor changes |
|
467
|
Wed Jan 6 15:51:58 2016 |
Larry Byars | Use of Channel Cascading in drs_exam.cpp | Hello Stefan,
Here in Rockford, TN we just got
a new DRS4 evaluation board (Serail # 2612, |
|
466
|
Wed Dec 30 17:00:00 2015 |
Stefan Ritt | Dtap stops toggling after 40msec | While I can understand 1., I'm puzzeled
by 2.
If you put the chip in standby |
|
465
|
Wed Dec 30 16:25:35 2015 |
mony orbach | Dtap stops toggling after 40msec | Hi
|
|
464
|
Mon Dec 28 11:21:54 2015 |
mony orbach | Dtap stops toggling after 40msec | Hi Stefan
Thanks for your input.
We are in the process of assemble |
|
463
|
Mon Dec 28 11:05:15 2015 |
Stefan Ritt | Dtap stops toggling after 40msec | Thanks for posting the plots. It really
looks like the PLL is not working. I see
two possible reasons: 1) The PLLEN bit in |
|
462
|
Sun Dec 27 15:41:32 2015 |
mony orbach | Dtap stops toggling after 40msec | Hi
We have some measures to show (attached)
Dtap and Denable
Dtap+Denable |
|
Draft
|
Sun Dec 27 15:06:59 2015 |
mony orbach | Dtap stops toggling after 40msec | Hi
We have some meesurs to show (attached)
Dtap and Denable
Dtap+Denable |
|
460
|
Thu Dec 24 12:45:41 2015 |
Stefan Ritt | Dtap stops toggling after 40msec | I want to see the trace on the scope for
the DTAP, the REFCLK, the DENABLE and the
DWRITE. |
|
459
|
Thu Dec 24 10:51:31 2015 |
mony orbach | Dtap stops toggling after 40msec | my refclk is 1.25Mhz
what are the inputs and voltage
you need to see? |
|
458
|
Wed Dec 23 15:48:42 2015 |
Stefan Ritt | Dtap stops toggling after 40msec | No idea what you do wrong. I need to see
oscilloscope traces for all your inputs and
voltages. What is your REFCLK input? |
|
457
|
Wed Dec 23 15:38:14 2015 |
mony orbach | Dtap stops toggling after 40msec | Hi
the drs4 start to generate Dtap
signal after reset and standard configuration. |
|
456
|
Sat Dec 5 03:21:21 2015 |
Chris Thompson | PC software beyond Windows 7 | On a hunch, I tried downloading V 5.0.3
instead. This works, and I now have the oscilloscope
mode displaying signals! (just to make sure, |
|
455
|
Sat Dec 5 02:39:20 2015 |
Chris Thompson | PC software beyond Windows 7 | I tried restarting Windows 10 in a way
the allowed me to use "advanced startup
options" Option 7 suggested it was to |
|
454
|
Thu Nov 26 18:59:27 2015 |
Robert Adams | Saving histogram data | I would really love to be able to save
histogram data, though I have not been able
to do this. I could take a screenshot and |
|
453
|
Wed Nov 25 17:36:25 2015 |
Chris Thompson | PC software beyond Windows 7 | I tried this suggestion of changing the
startup settings to ingore driver license
signing (as suggested in the post # 434), |
|
452
|
Wed Nov 25 08:20:47 2015 |
Stefan Ritt | PC software beyond Windows 7 | Have a look here elog:434
|
|
451
|
Wed Nov 25 02:52:35 2015 |
Chris Thompson | PC software beyond Windows 7 | I am new to this forum. I have ordered
a DRS4 evaluation board for doing experiments
with very fast PET detectors. It has not |
|
450
|
Thu Nov 5 00:18:42 2015 |
Will Flanagan | Latest macro for DRS4 V5 | Hi Stefan,
This is absolutely perfect.
Thanks, |
|
449
|
Wed Nov 4 15:40:10 2015 |
Stefan Ritt | Latest macro for DRS4 V5 | Have a look here: elog:361
|
|
448
|
Tue Nov 3 23:15:38 2015 |
Will Flanagan | Latest macro for DRS4 V5 | I should of course mention that I looked
through the DRS4 website and didn't see
anything obvious: https://www.psi.ch/drs/evaluation-board |
|
447
|
Tue Nov 3 22:37:56 2015 |
Will Flanagan | Latest macro for DRS4 V5 | Hi DRS4 Experts,
I have an extremely naive question:
Is there any official macro to unpack the |
|
Draft
|
Wed Oct 7 13:06:34 2015 |
Ilja Bekman | Voltage Calibration with signal on the input | |
|
445
|
Wed Aug 19 15:07:53 2015 |
Martin Petriska | QtPALS | There is software for DRS4 board and positron
lifetime measurement availiable. Still in
beta but works. Its usable for measuring |
|
444
|
Fri Aug 7 20:32:15 2015 |
Felix Bachmair | DRS4 | Hi
Did you copy the udev rule 41-drs.rules
into /etc/udev/rules.d/ ? |
|
443
|
Fri Aug 7 18:41:37 2015 |
dante | DRS4 | Hi
I have just installed DRS4, but
when I try to view it from the USB it don't |
|
442
|
Thu Jul 23 13:46:12 2015 |
Stefan Ritt | Measure the time between different samples | > Hi,
> I have a question using a data acquisition
card base on DRS4 chip. How can I measure |
|
441
|
Mon Jul 20 09:25:38 2015 |
Chenfei Yang | Measure the time between different samples | Hi,
I have a question using a data acquisition
card base on DRS4 chip. How can I measure |
|
440
|
Tue Jul 7 09:29:21 2015 |
Felix Bachmair | Creation of Object files | Yes of course no problem.
You can download via github https://github.com/veloxid/DRS4-v5-shared and |
|
439
|
Mon Jul 6 19:25:27 2015 |
Stefan Ritt | Creation of Object files | Anyhow it would be nice if you just post
your Makefile here, which runs with the standard
distribution, so people can use it if needed. |
|
438
|
Mon Jul 6 11:30:56 2015 |
Felix Bachmair | Creation of Object files | Hi Stefan,
That's fine for me. I thought
it might be interesting for others as well.. |
|
437
|
Fri Jul 3 17:13:27 2015 |
Stefan Ritt | Creation of Object files | Hi Felix,
the distribution does not contain
any binaries, since there are too many Linux |
|
436
|
Thu Jul 2 13:20:51 2015 |
Felix Bachmair | Creation of Object files | HI,
We are using the DRS4 Board in
the EUDAQ framework [1]. We wrote a a Producer |
|
435
|
Thu Jul 2 08:53:17 2015 |
Felix Bachmair | Issue with Trigger rates below ~100Hz | Hi,
We did a further investigation
of this problem: |
|
434
|
Fri Jun 19 12:32:10 2015 |
Gregor Kramberger | drs 5.03 and windows 8.1 |
|
|
433
|
Thu Jun 18 17:33:05 2015 |
Gregor Kramberger | drs 5.03 and windows 8.1 | I have problems with driver installation
on windows 8.1 (software version 5.03).
I have sen that that has been an issue before |
|
432
|
Tue Jun 16 22:26:41 2015 |
Stefan Ritt | DRS4 Evaluation Board Osc Application | There is a horizontal position slider in
the "Horizontal" box on the right
side below the trigger delay. Use it. |
|
431
|
Tue Jun 16 20:45:54 2015 |
Michael Buadelk | DRS4 Evaluation Board Osc Application | Hi, I have a DRS4 v5 evaluation board and
I have a novice question about the oscilliscop
application. When I connect it to a photo-detector |
|
430
|
Fri Jun 5 13:32:03 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | Actually we should take this offline not to
pester other DRS users which are not interested
in this topic. Please call me directly (3728) |
|
429
|
Fri Jun 5 13:29:55 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | Do the following:
Use the TRG OUT of the evaluation board as |
|
428
|
Fri Jun 5 13:15:35 2015 |
Felix Bachmair | DRS4 firmware UCF constraints | Hi Stefan,
No we only use one evaluation board. We use
the evaluation board as a part of our beam |
|
427
|
Fri Jun 5 12:07:38 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | I presume you have several evaluation boards
and want to run them in sync, right?
|
|
426
|
Wed Jun 3 09:07:38 2015 |
Stefan Ritt | Peculiar behavior of time values for Rev5 DRS4 EB | First of all, you should not use new boards
with old software. I try to keep the current
software compatible with old boards, but |
|
425
|
Tue May 26 11:27:27 2015 |
Felix Bachmair | DRS4 firmware UCF constraints | > > Hello, I'm using two DRS4 rev.5 boards
for 8ch readout and triggering.
> >
|
|
424
|
Sun May 24 09:34:27 2015 |
Peter Steinberg | Peculiar behavior of time values for Rev5 DRS4 EB | Hi -
I am setting up a new DRS4 rev5
but using drivers and software we were recently |
|
423
|
Sat May 23 11:03:20 2015 |
Felix Bachmair | Issue with Trigger rates below ~100Hz | Hi
We are working with the DRS 4 V5
version and we investigated an issue with |
|
422
|
Fri May 22 14:25:45 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | > Hello, I'm using two DRS4 rev.5 boards for
8ch readout and triggering.
>
|
|
421
|
Tue May 19 14:14:45 2015 |
Ilja Bekman | DRS4 firmware UCF constraints | Hello, I'm using two DRS4 rev.5 boards for
8ch readout and triggering.
|
|
420
|
Wed May 13 16:25:24 2015 |
Stefan Ritt | transparent-mode voltage | To get the good linearity, you need indeed
ROFS = 1.05V. With a O-OFS of 0.9V, a zero
input signal would give you DRS_OUT+=1.05V |
|
419
|
Wed May 13 16:13:07 2015 |
Chenfei Yang | transparent-mode voltage | If using a ROFS of 0.9V, the input would
not between 1.05V~2.05V better non-linearity
area. Is that appropriate? |
|
418
|
Wed May 13 12:52:22 2015 |
Chenfei Yang | transparent-mode voltage | Yes. I use exactly the same scheme as you
mentioned. I'll try your solution.
|
|
417
|
Wed May 13 12:34:49 2015 |
Stefan Ritt | transparent-mode voltage | There might be a solution. How do you bias
th input of the
DRS4 chip? If you use a scheme as described |
|
416
|
Wed May 13 10:27:43 2015 |
Chenfei Yang | transparent-mode voltage | I'm using an AD9252, 0.9V common mode
voltage is suggested and I already use 8
un-switchable level shifters. Just as you |
|
415
|
Wed May 13 10:16:40 2015 |
Stefan Ritt | transparent-mode voltage | I see your point. Actually I will soon
have the same issue since we design right
now a board with an AD9637 using the transparent |
|
414
|
Wed May 13 09:55:09 2015 |
Chenfei Yang | transparent-mode voltage | Here's the problem. My external ADC
has 2Vpp differtial input voltage range.
And the common-mode voltage of the inputs |
|
413
|
Wed May 13 09:45:51 2015 |
Stefan Ritt | transparent-mode voltage | The ROFS signal has no effect in the transparent
mode, so you have to adjust O_OFS between
sampling and transparent mode accordingly. |
|
412
|
Wed May 13 09:31:18 2015 |
Chenfei Yang | transparent-mode voltage | Hello Mr. Stefan Ritt
For DRS4 differential inputs
ranges form 500mV to 1100mV, with ROFS set |
|
411
|
Wed May 13 08:19:53 2015 |
Stefan Ritt | Getting Trigger Source | DRSBoard::GetTriggerSource() simply returns
what has been enabled via DRSBoard::SetTriggerSource().
The actual source which causes the trigger |
|
410
|
Wed May 13 01:07:36 2015 |
Cosmin Deaconu | DRS4 Evaluation Board + Powered USB Hub | I am trying to use 4 evaluation boards
with a powered USB hub (since eventually,
I will have to do this on a laptop). |
|
409
|
Wed May 13 00:52:51 2015 |
Cosmin Deaconu | Getting Trigger Source | I'd like to be able to know which channel
(0,1,2,3 or external) was responsible for
the trigger. DRSBoard::GetTriggerSource() |
|
408
|
Tue Apr 21 13:06:39 2015 |
Stefan Ritt | DRS4 Evaluation Board Baseline/Voltage Calibration | Sure, for a V3 board you need a pre-V5
software, but I assumed Julien had a V5 board.
|
|
407
|
Tue Apr 21 13:03:38 2015 |
Daniel Stricker-Shaver | DRS4 Evaluation Board Baseline/Voltage Calibration | I also use Ubuntu 14.04 LTS and for my
V3 borad I have to use drsosc 4.x or ealier
to perform the calibration. |
|
406
|
Tue Apr 21 12:52:18 2015 |
Stefan Ritt | DRS4 Evaluation Board Baseline/Voltage Calibration | 1) I tried to cablirate a V5 board with
drsosc 5.0.3 and it just worked fine for
me. No idea what went wrong in your case. |
|
405
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Tue Apr 21 12:01:45 2015 |
Stefan Ritt | DRSBoard::SetTriggerSource | Your first assumption is correct, e.g.
source = 00000000'00000001
= 0x0001 ==> CH1 |
|
404
|
Mon Apr 20 13:08:24 2015 |
Stefan Ritt | Clock settings in daisy chain DAQ | The resolution coming from the sampling
rate goes into these numbers, but just marginally.
At 5 GSPS, you get a few ps reolution, while |
|
403
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Fri Apr 17 10:07:38 2015 |
Simon Weingarten | Clock settings in daisy chain DAQ | Hi Stefan,
do you know how these numbers (400ps
and 60ps) scale with the sampling rate? The |
|
402
|
Thu Apr 9 11:46:33 2015 |
Felix Bachmair | DRSBoard::SetTriggerSource | Hi
I have a question about the function
SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp) |
|
401
|
Sun Apr 5 22:16:48 2015 |
Julien Wulf | DRS4 Evaluation Board Baseline/Voltage Calibration | Hi,
I`m trying to calibrate my DRS4
evoluation board to an input range of 0-1V |
|
400
|
Thu Mar 19 07:37:52 2015 |
Daniel Stricker-Shaver | Running 2 instances of a DRS DAQ program | I don't know if it helps, but we measured
the time resolution between two independendly
running v3 boards using a single PC (latest |
|
399
|
Tue Mar 17 02:53:26 2015 |
Stefan Ritt | Running 2 instances of a DRS DAQ program | I never had in mind running two systems
in parallel, that's why the code claims
all interfaces when started. You have to |
|
398
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Mon Mar 16 16:07:39 2015 |
Hermann-Josef Mathes | Running 2 instances of a DRS DAQ program | Hi,
we want to run two instances of
our little DRS DAQ program but obviously |
|
397
|
Fri Feb 13 10:12:16 2015 |
Andrzej Grzeszczuk | drs4 and root | Hello,
I compiled base file for drs system
(DRS.cpp) to root framework (root.cern.ch) |
|
396
|
Fri Jan 16 14:12:19 2015 |
Stefan Ritt | Mac OSX Yosemite 10.10 | > Hello,
>
> I can compile version 5.0.3 of DRS4sc on |
|
395
|
Fri Jan 16 13:29:05 2015 |
Rainer Hentges | Mac OSX Yosemite 10.10 | Hello,
I can compile version 5.0.3 of DRS4sc on |
|
394
|
Tue Nov 25 14:06:34 2014 |
Stefan Ritt | Raspberry Pi drsosc does not exit properly |
|
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393
|
Mon Nov 17 16:36:18 2014 |
Mickey Chiu | Raspberry Pi drsosc does not exit properly | When running drsosc on a raspberry pi,
it seems the exit doesn't seem to work at
all. This is true for the "exit" |
|
392
|
Sun Oct 19 14:36:54 2014 |
Chris Tully | coverting the xml file format into binary | Hi,
Is there a straightforward
way to convert the xml file format into the |
|
391
|
Thu Oct 16 16:16:12 2014 |
Stefan Ritt | binary files time calibration header in drs-5.0.2 | > Dear Stefan
>
> I have a problem considering binary data |
|
390
|
Thu Oct 16 16:15:16 2014 |
Stefan Ritt | binary files with more than 4 drs board ver. 5.0.2 | > Dear Stefan
>
> after having some problems with writing |
|
389
|
Wed Oct 15 12:15:58 2014 |
Stefan Ritt | Clock settings in daisy chain DAQ | Here is the full version
of the program with clock daisy-chaining.
Before switching to the external clock, it |
|
388
|
Wed Oct 15 11:34:43 2014 |
Simon Weingarten | Clock settings in daisy chain DAQ |
|
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387
|
Wed Oct 15 10:52:58 2014 |
Stefan Ritt | Clock settings in daisy chain DAQ |
|
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386
|
Wed Oct 15 10:14:32 2014 |
Simon Weingarten | Clock settings in daisy chain DAQ | Hi,
I'm currently working on a little
DAQ system with four DRS evaluation boards. |
|
385
|
Tue Oct 14 16:51:37 2014 |
Stephane Debieux | USB Microcontroller firmware |
|
|
384
|
Tue Oct 14 16:38:14 2014 |
Stefan Ritt | USB Microcontroller firmware |
|
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383
|
Tue Oct 14 16:34:45 2014 |
Stephane Debieux | USB Microcontroller firmware |
|
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382
|
Tue Oct 14 16:29:12 2014 |
Stefan Ritt | USB Microcontroller firmware |
|
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381
|
Tue Oct 14 16:21:07 2014 |
Stephane Debieux | USB Microcontroller firmware |
|
|
380
|
Mon Oct 13 17:14:58 2014 |
Stefan Ritt | USB Microcontroller firmware |
|
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379
|
Mon Oct 13 17:08:40 2014 |
Stephane Debieux | USB Microcontroller firmware |
|
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378
|
Mon Oct 13 16:46:56 2014 |
Stefan Ritt | USB Microcontroller firmware |
|
|
377
|
Tue Oct 7 14:09:02 2014 |
Stephane Debieux | USB Microcontroller firmware | Hi,
I'm trying to recompile the USB microcontroller
firmware starting from the drs_eval.c file |
|
376
|
Mon Sep 22 15:04:37 2014 |
Stefan Ritt | Timing Calibration Fail |
|
|
375
|
Mon Sep 22 14:52:21 2014 |
Stefan Ritt | compilation error for v5.0.2 |
|
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374
|
Mon Sep 15 16:24:41 2014 |
Hannes Wachter | Timing Calibration Fail | Hi,
has anyone experienced a shutdown
of the DRSosc.exe or DRScl.exe when executing |
|
373
|
Fri Sep 12 16:38:24 2014 |
Dmitry Hits | compilation error for v5.0.2 |
|
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372
|
Fri Sep 12 16:08:49 2014 |
Stefan Ritt | compilation error for v5.0.2 |
|
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371
|
Fri Sep 12 14:57:22 2014 |
Dmitry Hits | compilation error for v5.0.2 | Hi,
I am getting the following compilation
error when trying to compile version 5.0.2 |
|
370
|
Fri Sep 12 13:41:43 2014 |
Stefan Ritt | synchronizing two DRS4 evaluation boards readout with one computer |
|
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369
|
Fri Sep 12 13:37:42 2014 |
Dmitry Hits | synchronizing two DRS4 evaluation boards readout with one computer |
|
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368
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Fri Sep 12 13:00:04 2014 |
Stefan Ritt | synchronizing two DRS4 evaluation boards readout with one computer |
|
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367
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Fri Sep 12 11:52:21 2014 |
Dmitry Hits | synchronizing two DRS4 evaluation boards readout with one computer | Hi everyone,
Has anyone tried to synchronize 2
(two) DRS4 evaluation boards readout by the |
|
366
|
Tue Aug 26 14:16:26 2014 |
Roman Gredig | binary files with more than 4 drs board ver. 5.0.2 | Dear Stefan
after having some problems with writing binary |
|
365
|
Tue Aug 26 12:32:21 2014 |
Stefan Ritt | 10GSps on DRS4 Evm with delay cables |
|
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364
|
Thu Aug 21 11:03:36 2014 |
Martin Petriska | 10GSps on DRS4 Evm with delay cables | Hi, I read its possible to use channels
2,4,6 to extend 200ns to 400ns (1024bins
to 2048). |
|
363
|
Wed Aug 13 20:17:19 2014 |
Roman Gredig | binary files time calibration header in drs-5.0.2 | Dear Stefan
I have a problem considering binary data |
|
362
|
Wed Jul 30 17:05:38 2014 |
Stefan Ritt | drsosc binary to cern ROOT file conversion |
|
|
361
|
Wed Jul 30 17:05:06 2014 |
Stefan Ritt | ROOT program to decode binary data from DRSOsc |
|
|
360
|
Wed Jul 30 11:38:58 2014 |
Tsutomu Nagayoshi | Sampling speed of DRS4 Board ver4 | Hello!
I have a question concerning the
sampling speed of the DRS4 evaluation board. |
|
359
|
Wed Jul 16 12:10:19 2014 |
Stefan Ritt | change cascading from 1024 to 2048 bins for each input channel |
|
|
358
|
Mon Jul 14 19:03:05 2014 |
Yves Bianga | change cascading from 1024 to 2048 bins for each input channel | Hello,
I want to ask
whether it is possible to modify a Evaluation |
|
357
|
Fri Jun 27 11:23:19 2014 |
ChengMing Du | drsosc binary to cern ROOT file conversion |
|
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356
|
Mon Jun 16 15:35:59 2014 |
Osip Lishilin | Announcement of new Evaluation Board V5 |
|
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355
|
Thu Jun 12 17:16:13 2014 |
Stefan Ritt | CalibrationWaveform |
|
|
354
|
Thu Jun 12 12:46:00 2014 |
Stefan Ritt | DRS eval bord v5 Timing | > a) Calibration:
> I am using 4 boards daisy chained. To achieve
optimal time resolution I did first a voltage |
|
353
|
Thu Jun 12 12:40:03 2014 |
Roman Gredig | DRS eval bord v5 Timing | Dear Stefan
I have two questions concerning the best |
|
352
|
Wed Jun 11 11:13:50 2014 |
Stefan Ritt | Announcement of new Evaluation Board V5 |
|
|
351
|
Mon Jun 9 12:03:26 2014 |
Osip Lishilin | Announcement of new Evaluation Board V5 |
|
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350
|
Thu May 29 04:22:43 2014 |
Toshihiro Nonaka | CalibrationWaveform | I'm writing the drs_exam.cpp to use multi-boards(v3,
firmware:4.0.0), and taking data succeeded.
But I have several questions about function |
|
349
|
Tue May 27 16:07:17 2014 |
Stefan Ritt | Spikes in DRS4 data on custom baord. |
|
|
348
|
Tue May 27 13:46:18 2014 |
Dominik Neise | Spikes in DRS4 data on custom baord. | We see quite some spikes in our DRS4 sampled
data in FACT. We see different types
of spikes: |
|
347
|
Mon May 19 08:04:57 2014 |
Stefan Ritt | simultaneous writing and reading with region of interest mode? |
|
|
346
|
Fri May 16 14:04:47 2014 |
Benjamin LeGeyt | simultaneous writing and reading with region of interest mode? | Hello!
We're developing electronics based
on the DRS4 to read out a breast PET scanner |
|
345
|
Tue May 13 23:08:50 2014 |
Stefan Ritt | drsosc binary to cern ROOT file conversion |
|
|
344
|
Tue May 13 22:03:47 2014 |
Luka Pavelic | drsosc binary to cern ROOT file conversion | Thank you for your fast and very helpful
replay.
|
|
343
|
Tue May 13 19:39:36 2014 |
Stefan Ritt | drsosc binary to cern ROOT file conversion |
|
|
342
|
Tue May 13 19:34:58 2014 |
Luka Pavelic | drsosc binary to cern ROOT file conversion | Hi,
Does anybody have program for conversion |
|
341
|
Thu Apr 24 23:03:25 2014 |
Carlo Stella | drs_exam project fail to compile |
|
|
340
|
Thu Apr 17 12:02:28 2014 |
Wang | The first channel is wrong. | Hi, |
|
339
|
Wed Apr 16 10:24:55 2014 |
Stefan Ritt | DRS4 Evalboard V5 with Windows7Pro64bit | >
> Dear Stefan
>
|
|
338
|
Wed Apr 16 08:30:32 2014 |
Stefan Ritt | why is the first channel output error? |
|
|
337
|
Wed Apr 16 08:20:36 2014 |
Stefan Ritt | drs_exam project fail to compile |
|
|
336
|
Wed Apr 16 03:22:43 2014 |
Wang | why is the first channel output error? | Hi,
|
|
335
|
Tue Apr 15 18:35:41 2014 |
Carlo Stella | drs_exam project fail to compile | Hi,
when I try to compile drs_exam project
my computer give me this output: |
|
334
|
Thu Apr 10 14:45:12 2014 |
Roman Gredig | DRS4 Evalboard V5 with Windows7Pro64bit |
Dear Stefan
|
|
333
|
Thu Mar 6 11:12:44 2014 |
Stefan Ritt | Software drs-5.0.0 fails to compile (drsosc) |
|
|
332
|
Wed Mar 5 21:54:13 2014 |
Hermann-Josef Mathes | Software drs-5.0.0 fails to compile (drsosc) | Hi,
the latest software drs-5.0.0.tar.gz
fails to compile on my freshly installed |
|
331
|
Tue Feb 18 14:12:37 2014 |
Stefan Ritt | Announcement of new Evaluation Board V5 |
|
|
330
|
Wed Feb 5 13:41:42 2014 |
Stefan Ritt | Repeated time calibration |
|
|
329
|
Wed Jan 15 17:37:21 2014 |
Stefan Ritt | DRS4 installation on Windows 8 issues |
|
|
328
|
Wed Jan 15 17:34:55 2014 |
Stefan Ritt | DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program |
|
|
327
|
Wed Jan 15 17:11:14 2014 |
Stefan Ritt | Some bug fixes and questions |
|
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326
|
Wed Jan 15 17:02:58 2014 |
Stefan Ritt | Some bug fixes and questions |
|
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325
|
Wed Jan 15 16:15:00 2014 |
Stefan Ritt | Some bug fixes and questions |
|
|
324
|
Wed Jan 15 15:48:55 2014 |
Stefan Ritt | USB connection stops | Hi,
finally I found some time to look into this |
|
323
|
Wed Jan 15 14:20:51 2014 |
Stefan Ritt | Announcement of new Evaluation Board V5 | Dear DRS community,
starting from this year, we ship
the new evaluation board V5. This board has |
|
322
|
Thu Jan 9 11:02:46 2014 |
Stefan Ritt | v5 software with v4 board calibration |
|
|
321
|
Thu Jan 9 10:58:19 2014 |
Martin Petriska | v5 software with v4 board calibration | Hi
Question:
In v4 board, which channel has best |
|
320
|
Tue Dec 17 08:45:32 2013 |
Stefan Ritt | synchronisation of readouts of two boards for offline analysis |
|
|
319
|
Mon Dec 16 11:09:25 2013 |
Dmitry Hits | synchronisation of readouts of two boards for offline analysis |
|
|
318
|
Fri Dec 13 11:37:58 2013 |
Stefan Ritt | input protection in DRS4 evaluation board |
|
|
317
|
Fri Dec 13 10:37:18 2013 |
Dmitry Hits | input protection in DRS4 evaluation board | Dear Stefan
Last month I was using a DRS4 evaluation
board to digitise the signal from the charged |
|
316
|
Tue Dec 10 14:54:46 2013 |
Stefan Ritt | measurement range |
|
|
315
|
Tue Dec 10 14:48:42 2013 |
ismail okan atakisi | measurement range | I m trying to measure lifetime in our lab
and I intend to take
measurement with DRS4 at that point |
|
314
|
Tue Nov 26 15:38:13 2013 |
Stefan Ritt | reducing sampling speed |
|
|
313
|
Tue Nov 26 15:36:39 2013 |
Dmitry Hits | reducing sampling speed | Dear Stefan
Is there an easy way to reduce sampling
speed below 0.7 GSPS? I would like to record |
|
312
|
Thu Nov 21 14:45:56 2013 |
Stefan Ritt | Cascading of channels |
|
|
311
|
Thu Nov 21 14:35:57 2013 |
Schablo | Cascading of channels |
|
|
310
|
Wed Nov 20 08:16:10 2013 |
Stefan Ritt | DRSOsc at Mac OS X Mavericks |
|
|
309
|
Tue Nov 19 21:49:37 2013 |
Andriy Zatserklyaniy | DRSOsc at Mac OS X Mavericks |
|
|
308
|
Tue Nov 19 09:09:01 2013 |
Stefan Ritt | DRSOsc at Mac OS X Mavericks |
|
|
307
|
Tue Nov 19 04:33:22 2013 |
Andriy Zatserklyaniy | DRSOsc at Mac OS X Mavericks | I installed Mac OS package on macbook
(late 2013). DRSOsc starts to write file
but freezes; need to be restarted to restore |
|
306
|
Mon Nov 18 16:00:26 2013 |
Stefan Ritt | synchronisation of readouts of two boards for offline analysis |
|
|
305
|
Mon Nov 18 15:49:01 2013 |
Dmitry Hits | synchronisation of readouts of two boards for offline analysis | Dear Stefan,
I am trying to synchronise the readout
of two test boards, one is the DRS4 test |
|
304
|
Mon Nov 18 11:20:15 2013 |
Dmitry Hits | flickering screen for drsosc |
|
|
303
|
Thu Nov 14 12:51:56 2013 |
Stefan Ritt | Cascading of channels |
|
|
302
|
Thu Nov 14 11:39:06 2013 |
Schablo | Cascading of channels | Hello, I want use cascading
of channels for 2048 cell - SetChannelConfig(0,8,4),
but i can't understand how . Please, help |
|
301
|
Wed Nov 6 16:35:42 2013 |
Stefan Ritt | |
|
|
300
|
Wed Nov 6 12:25:31 2013 |
Stefan Ritt | flickering screen for drsosc |
|
|
299
|
Wed Nov 6 11:53:28 2013 |
Dmitry Hits | flickering screen for drsosc | Hi,
I have install drs software on ASUS |
|
298
|
Mon Oct 21 14:43:21 2013 |
Stephane Debieux | DRS4 analog outputs - interfacing DRS4 to AD9222 ADC | Hi,
I wish to interface the DRS4 with
the 8-channel ADC AD9222 (or AD9637). |
|
297
|
Wed Sep 25 14:42:00 2013 |
Akira Okumura | USB connection stops | Hello Andrey,
Thank you for your advise. But we never terminated |
|
296
|
Mon Sep 23 09:51:48 2013 |
Andrzej Rychter | Sampling Frequency: DRS4 eval board |
|
|
295
|
Mon Sep 23 09:26:56 2013 |
Stefan Ritt | Sampling Frequency: DRS4 eval board |
|
|
294
|
Mon Sep 23 09:22:52 2013 |
Andrzej Rychter | Sampling Frequency: DRS4 eval board | Is it possible to set sampling frequency
at 100 MHz in DRS4 eval board? Trying to
set 0.1GHz in Osci program results in around |
|
293
|
Wed Sep 11 02:41:28 2013 |
Andrey Kuznetsov | USB connection stops | Hi,
although I don't have a chance to test your |
|
292
|
Tue Sep 10 10:31:30 2013 |
Akira Okumura | USB connection stops | Hello the DRS4 team,
I and some of my colleagues are using DRS4 |
|
291
|
Mon Sep 9 06:49:36 2013 |
Andrey Kuznetsov | Some bug fixes and questions | The DRSCallback *pcb is
missing an if statement in the code when
DRS Oscilloscope software isn't used when |
|
290
|
Thu Sep 5 10:01:00 2013 |
Andrey Kuznetsov | Some bug fixes and questions | #11 0x080589de in DRSBoard::GetWave (this=0xb7456008,
chipIndex=0, channel=0 '\000', waveform=0x40f24000,
responseCalib=true, triggerCell=207, wsr=0, |
|
289
|
Wed Aug 28 13:07:51 2013 |
Andrey Kuznetsov | Some bug fixes and questions | For http://www.psi.ch/drs/DocumentationEN/manual_rev20.pdf:
0 0x02 15..8 board_type 5 for DRS4
USB Evaluation Board 1.1 ---> should instead |
|
288
|
Wed Aug 28 04:05:48 2013 |
lengchongyang | |
|
|
287
|
Tue Aug 27 16:14:49 2013 |
lengchongyang | | Hello everyone!I'm a
new user of DRS4 board,but it seems that |
|
286
|
Mon Aug 12 22:18:39 2013 |
Stefan Ritt | add an average ability to the Scope |
|
|
285
|
Mon Aug 12 15:08:17 2013 |
tmiron alon | add an average ability to the Scope |
|
|
284
|
Wed Aug 7 15:20:33 2013 |
Hermann-Josef Mathes | Repeated time calibration |
|
|
283
|
Wed Aug 7 15:10:57 2013 |
Stefan Ritt | Repeated time calibration |
|
|
282
|
Wed Aug 7 15:05:59 2013 |
Hermann-Josef Mathes | Repeated time calibration | Hi,
is there any (obvious) reason why |
|
281
|
Mon Jul 29 06:04:45 2013 |
Stefan Ritt | add an average ability to the Scope |
|
|
280
|
Sun Jul 28 09:52:25 2013 |
tmiron alon | add an average ability to the Scope |
|
|
279
|
Thu Jul 25 01:31:29 2013 |
Andrey Kuznetsov | Evaluation Board Behavior |
|
|
278
|
Tue Jul 23 22:42:31 2013 |
alonzi | Evaluation Board Behavior |
|
|
277
|
Tue Jul 23 22:35:08 2013 |
Stefan Ritt | Evaluation Board Behavior |
|
|
276
|
Tue Jul 23 22:31:08 2013 |
alonzi | Evaluation Board Behavior | Working with the DRS evaluation board we
noticed some funny behavior: See attatchment
1. In about 1% of scope traces we see the |
|
275
|
Tue Jul 16 16:25:43 2013 |
Stefan Ritt | add an average ability to the Scope |
|
|
274
|
Tue Jul 16 10:02:28 2013 |
tmiron alon | add an average ability to the Scope |
|
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273
|
Tue Jul 9 14:00:49 2013 |
Dmitry Hits | cannot save in binary format |
|
|
272
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Tue Jul 9 12:23:06 2013 |
Stefan Ritt | cannot save in binary format |
|
|
271
|
Tue Jul 9 11:40:00 2013 |
Dmitry Hits | cannot save in binary format | Hi,
I would like to save the waveform
in a binary format. When I click Save then |
|
270
|
Sat Jul 6 06:10:38 2013 |
Stefan Ritt | Missing methods in drs-4.0.1.tar.gz |
|
|
269
|
Fri Jul 5 12:46:45 2013 |
Hermann-Josef Mathes | Missing methods in drs-4.0.1.tar.gz | Hi,
while trying to create python bindings
for the DRS stuff using SWIG 2.0.4, two undefined |
|
268
|
Thu Jul 4 10:14:32 2013 |
Stefan Ritt | add an average ability to the Scope |
|
|
267
|
Thu Jul 4 10:01:06 2013 |
tmiron alon | add an average ability to the Scope |
|
|
266
|
Thu Jul 4 09:17:31 2013 |
Stefan Ritt | add an average ability to the Scope |
|
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265
|
Thu Jul 4 09:07:24 2013 |
tmiron alon | add an average ability to the Scope |
|
|
264
|
Thu Jul 4 08:54:25 2013 |
Stefan Ritt | add an average ability to the Scope |
|
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263
|
Thu Jul 4 08:32:11 2013 |
tmiron alon | add an average ability to the Scope |
|
|
262
|
Tue Jun 18 14:19:39 2013 |
Stefan Ritt | ROOT program to decode binary data from DRSOsc | Please find attached a simple ROOT based
program (http://root.cern.ch) to decode binary
data from the DRSOsc program. It assumes |
|
261
|
Mon Jun 10 16:24:21 2013 |
Stefan Ritt | add an average ability to the Scope |
|
|
260
|
Mon Jun 10 14:09:13 2013 |
tmiron alon | add an average ability to the Scope |
|
|
259
|
Fri Jun 7 11:44:17 2013 |
tmiron alon | thank you |
|
|
258
|
Fri Jun 7 10:22:48 2013 |
Stefan Ritt | |
|
|
257
|
Sun May 26 13:08:52 2013 |
tmiron alon | | Hallo,
I'm using DRS4 Evaluation Board Rev
4.0 and I'm trying to change the output |
|
256
|
Sat May 25 21:03:22 2013 |
Stefan Ritt | DRS4- analog pulse counting |
|
|
255
|
Sat May 25 12:45:46 2013 |
Enrico Conti | mac osx 10.6 | > > I made some progress. Understood what
was wrong in the make phase. You have only
to add the option -arch i386 in the CFLAGS |
|
254
|
Fri May 24 18:20:14 2013 |
Stefan Ritt | mac osx 10.6 | > I made some progress. Understood what was
wrong in the make phase. You have only to
add the option -arch i386 in the CFLAGS line |
|
253
|
Fri May 24 17:58:07 2013 |
Enrico Conti | mac osx 10.6 | > > >
> > > it looks like 64bit vs 32bit problem,
you have to compile all libraries for the |
|
252
|
Tue May 21 18:30:11 2013 |
Enrico Conti | mac osx 10.6 | > > >
> > > it looks like 64bit vs 32bit problem,
you have to compile all libraries for the |
|
251
|
Tue May 21 17:51:09 2013 |
Stefan Ritt | mac osx 10.6 | > >
> > it looks like 64bit vs 32bit problem,
you have to compile all libraries for the |
|
250
|
Tue May 21 17:48:45 2013 |
Enrico Conti | mac osx 10.6 | >
> it looks like 64bit vs 32bit problem, you
have to compile all libraries for the same |
|
249
|
Tue May 21 17:45:05 2013 |
Enrico Conti | mac osx 10.6 | >
> Can it be that you have a old PowerPC MAC?
I have no experience with that, but probably |
|
248
|
Tue May 21 13:32:13 2013 |
Martin Petriska | mac osx 10.6 | > Hi,
>
> I would like to use the DRS4 with my macbook |
|
247
|
Tue May 21 13:25:41 2013 |
Stefan Ritt | mac osx 10.6 | > Hi,
>
> I would like to use the DRS4 with my macbook |
|
246
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Tue May 21 12:39:00 2013 |
Enrico Conti | mac osx 10.6 | Hi,
I would like to use the DRS4 with my macbook |
|
245
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Mon May 20 08:42:16 2013 |
Osip Lishilin | DRS4- analog pulse counting |
|
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244
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Wed May 8 19:50:01 2013 |
Andrey Kuznetsov | DRS4 installation on Windows 8 issues | I'm also
having trouble installing drivers and running
DRSOsc program on another computer running |
|
243
|
Wed May 8 06:07:52 2013 |
Andrey Kuznetsov | DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program | Hi,
I have an old v2.0 board that I just
upgraded firmware on using v4.0.0 download |
|
242
|
Mon Apr 22 15:52:53 2013 |
Stefan Ritt | effect of jitter/alignment between SRCLK and ADC clock |
|
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241
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Mon Apr 22 15:33:28 2013 |
Benjamin LeGeyt | effect of jitter/alignment between SRCLK and ADC clock | Hello!
let me apologize in advance if this
has already been covered somewhere and I |
|
240
|
Fri Apr 12 08:38:17 2013 |
Stefan Ritt | code/details for optimal DRS4 timing calibration? |
|
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239
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Fri Apr 12 08:25:05 2013 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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238
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Thu Apr 11 23:32:57 2013 |
Jill Russek | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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237
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Thu Apr 11 22:41:13 2013 |
Bill Ashmanskas | code/details for optimal DRS4 timing calibration? | Hi Stefan,
Is either some example code or a
detailed written description available for |
|
236
|
Thu Apr 11 08:39:12 2013 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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235
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Wed Apr 10 22:41:21 2013 |
Jill Russek | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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234
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Mon Apr 8 18:11:02 2013 |
Dmitry Hits | binary to root | Hi,
Does anyone has a program that converts |
|
233
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Fri Apr 5 08:54:37 2013 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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232
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Fri Apr 5 02:21:33 2013 |
Jill Russek | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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231
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Thu Apr 4 11:32:21 2013 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
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230
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Thu Apr 4 11:21:04 2013 |
Stefan Ritt | Differences in Source Code |
|
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229
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Tue Mar 26 01:17:59 2013 |
Jill Russek | cascading -- DRS4 Osci.cpp & DRS.cpp |
All I'm trying to do is cascade one
input signal, though all available channels, |
|
228
|
Mon Mar 25 11:12:53 2013 |
Georg Winner | Differences in Source Code | I have noticed some differences in the
source code between Windows (4.0.0) and Linux
(4.0.1) Version. |
|
227
|
Wed Mar 6 13:08:03 2013 |
Stefan Ritt | Chip Test - Cell Error |
|
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226
|
Wed Mar 6 12:37:14 2013 |
Stefan Ritt | DRS4- analog pulse counting |
|
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225
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Wed Mar 6 12:35:38 2013 |
Osip Lishilin | DRS4- analog pulse counting | Hello,
Stefan. Have you implemented pulse counting
yet? |
|
224
|
Thu Feb 28 12:58:44 2013 |
Stefan Ritt | clock and trigger outs | > Hi,
> I am considering using the DRS4 evaluation
board as an ADC card for the wire chamber |
|
223
|
Thu Feb 28 10:47:14 2013 |
Dmitry Hits | clock and trigger outs | Hi,
I am considering using the DRS4 evaluation
board as an ADC card for the wire chamber |
|
222
|
Wed Feb 27 13:47:32 2013 |
Georg Winner | Chip Test - Cell Error | When starting Chip Test in DRS Command
Line Interface, I receive the following message:
Cell error on channel 1, cell |
|
220
|
Fri Feb 22 11:56:57 2013 |
Stefan Ritt | DRS4 trigger, different polarity |
|
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219
|
Fri Feb 22 11:46:17 2013 |
Yury Golod | DRS4 trigger, different polarity |
Normal
0
|
|
218
|
Wed Feb 13 17:03:53 2013 |
Stefan Ritt | Nonuniform sampling |
|
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217
|
Wed Feb 13 16:58:40 2013 |
Martin Petriska | Nonuniform sampling | Are there any plans to include reconstruction
of nonuniform sampling in DRS4 to get
uniformly sampled data? |
|
216
|
Tue Feb 5 14:38:35 2013 |
Stefan Ritt | variation of sampling capacitors |
|
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215
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Fri Feb 1 17:43:48 2013 |
Jinhong Wang | variation of sampling capacitors |
|
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214
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Thu Dec 27 18:15:14 2012 |
Jinhong Wang | variation of sampling capacitors |
|
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213
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Thu Dec 27 09:49:17 2012 |
Stefan Ritt | variation of sampling capacitors |
|
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212
|
Thu Dec 27 00:12:12 2012 |
Jinhong Wang | variation of sampling capacitors | Hi Stefan,
A quick question, what is the typical
variation of the sampling capacitors in DRS4? |
|
211
|
Fri Dec 14 21:49:29 2012 |
Stefan Ritt | EVM rev4 board trigger change and drs_example |
|
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210
|
Fri Dec 14 10:07:54 2012 |
Evgeni | DRS-4 trigger |
|
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209
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Fri Dec 14 10:07:14 2012 |
Evgeni | DRS-4 trigger |
|
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208
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Fri Dec 14 08:42:53 2012 |
Stefan Ritt | DRS-4 trigger |
|
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207
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Thu Dec 13 19:49:47 2012 |
Evgeni | DRS-4 trigger |
|
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206
|
Thu Dec 13 12:14:35 2012 |
Stefan Ritt | DRS-4 trigger |
|
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205
|
Thu Dec 13 12:03:29 2012 |
Evgeni | DRS-4 trigger | How to configure DRS oscilloscope for the
oscillations with an amplitude greater than
the value of the exposed |
|
204
|
Thu Dec 6 09:23:36 2012 |
Martin Petriska | EVM rev4 board trigger change and drs_example | I switched from rev 3 to rev 4 board,
but have some problems with triggering, board
is now waiting for trigger (rev.3 is working). |
|
203
|
Tue Dec 4 09:55:43 2012 |
Stefan Ritt | Question of drs4 using |
|
|
202
|
Tue Dec 4 09:50:11 2012 |
Zhongwei Du | Question of drs4 using |
|
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201
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Tue Dec 4 09:39:44 2012 |
Stefan Ritt | Question of drs4 using |
|
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200
|
Tue Dec 4 09:24:22 2012 |
Zhongwei Du | Question of drs4 using | When Denable and Dwrite is high , the voltage
of PLLOUT is 0 V. And the Dtap
is turn high with no delay when the Denable |
|
199
|
Mon Dec 3 11:40:35 2012 |
Gyuhee Kim | Another question about using multi boards. |
|
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198
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Mon Dec 3 09:18:09 2012 |
Stefan Ritt | Another question about using multi boards. |
|
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197
|
Mon Dec 3 08:32:28 2012 |
Gyuhee Kim | Another question about using multi boards. | Hi.
I asked about using multi boards |
|
196
|
Wed Nov 28 16:54:46 2012 |
Stefan Ritt | DRS Oscilloscope for Raspberry Pi and Mac OSX 10.8 | I made a pre-compiled package for Mac OSX
10.8 (Mountain Lion), so one should be able
to install the DRS Oscilloscope software |
|
195
|
Wed Nov 21 08:48:00 2012 |
Gyuhee Kim | Question for using Multi board |
|
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194
|
Wed Nov 21 08:38:26 2012 |
Stefan Ritt | Question for using Multi board |
|
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193
|
Wed Nov 21 08:34:52 2012 |
Gyuhee Kim | Question for using Multi board | Hi.
I have 2 DRS4 evaluation V4 boards, |
|
192
|
Tue Nov 13 11:26:32 2012 |
Stefan Ritt | GetWave |
|
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191
|
Thu Nov 1 20:46:53 2012 |
hongwei yang | DRS4 firmware |
|
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190
|
Thu Nov 1 20:32:03 2012 |
Stefan Ritt | DRS4 firmware |
|
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189
|
Thu Nov 1 20:25:53 2012 |
hongwei yang | DRS4 firmware |
|
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188
|
Thu Nov 1 20:21:44 2012 |
hongwei yang | DRS4 firmware |
|
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187
|
Thu Nov 1 20:17:42 2012 |
Stefan Ritt | DRS4 firmware |
|
|
186
|
Thu Nov 1 20:08:33 2012 |
hongwei yang | DRS4 firmware | Hi,
We are using drs4
board, but oscilloscope app will somehow |
|
185
|
Mon Oct 29 18:30:28 2012 |
Martin Petriska | GetWave | I have some question according to
GetWave function. In drs_exam.cpp simple
GetWave(0,0,wave_array[]) etc...is used. |
|
184
|
Fri Oct 12 14:09:37 2012 |
Stefan Ritt | DRS abbreviation |
|
|
183
|
Fri Oct 12 14:06:04 2012 |
Moritz von Witzleben | DRS abbreviation | Hello,
what is the abbreviation of DRS?
Thanks and kind Regards, |
|
182
|
Thu Oct 4 21:07:27 2012 |
Zach Miller | DRS5 |
|
|
181
|
Thu Oct 4 20:59:18 2012 |
Stefan Ritt | DRS5 |
|
|
180
|
Thu Oct 4 20:50:36 2012 |
Zach Miller | DRS5 | Hi,
Our group had previously heard that
a "DRS-5.0" might be on the horizon |
|
179
|
Wed Aug 29 16:57:49 2012 |
Zach Miller | DRS-4.0.0 DOScreen.cpp |
|
|
178
|
Wed Aug 29 16:45:36 2012 |
Stefan Ritt | DRS-4.0.0 DOScreen.cpp |
|
|
177
|
Wed Aug 29 16:42:42 2012 |
Zach Miller | DRS-4.0.0 DOScreen.cpp |
|
|
176
|
Wed Aug 29 10:52:44 2012 |
Stefan Ritt | DRS-4.0.0 DOScreen.cpp |
|
|
175
|
Tue Aug 28 17:52:45 2012 |
Zach Miller | DRS-4.0.0 DOScreen.cpp | Hi,
I found an old thread regarding a
fix for DOScreen.cpp for DRS-3.1.0, that |
|
174
|
Mon Aug 6 02:44:00 2012 |
Stefan Ritt | Calculation of loop filter parameters (R,C1and C1) for 1 GHz |
|
|
173
|
Wed Aug 1 17:42:32 2012 |
Mayank S. Rajguru | Calculation of loop filter parameters (R,C1and C1) for 1 GHz | Hi,
we are planning to use the DRS4 in
our board for 1 GHz sampling and digitization. |
|
172
|
Wed Jul 11 10:04:51 2012 |
Ivan Petrov | Problem compiling drs_exam.cpp on windows |
|
|
171
|
Tue Jul 10 13:15:00 2012 |
Stefan Ritt | Problem compiling drs_exam.cpp on windows |
|
|
170
|
Mon Jul 9 14:14:48 2012 |
Ivan Petrov | Problem compiling drs_exam.cpp on windows | Hello again. I have not got evaluation
board yet, but already faced some difficulties:)
I'm trying to compile drs_exam.cpp on Windows |
|
169
|
Mon Jun 25 14:21:13 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
|
|
168
|
Sat Jun 23 00:29:52 2012 |
Andrey Kuznetsov | triger for measuring time between pulses in channels |
|
|
167
|
Wed Jun 20 14:44:38 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
|
|
166
|
Wed Jun 20 14:36:01 2012 |
Ivan Petrov | triger for measuring time between pulses in channels |
|
|
165
|
Wed Jun 20 12:45:05 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
|
|
164
|
Wed Jun 20 10:40:21 2012 |
Ivan Petrov | triger for measuring time between pulses in channels |
|
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163
|
Wed Apr 25 13:42:37 2012 |
Stefan Ritt | DRS4 Initialization |
|
|
162
|
Mon Apr 23 10:38:51 2012 |
Guillaume Blanchard | DRS4 Initialization | Hello,
I am writing a VHDL code to drive
a DRS4 chip. |
|
161
|
Wed Mar 21 09:39:33 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
|
|
160
|
Wed Mar 21 09:33:00 2012 |
Martin Petriska | triger for measuring time between pulses in channels |
|
|
159
|
Tue Mar 20 16:33:50 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
|
|
158
|
Tue Mar 20 16:23:33 2012 |
Martin Petriska | triger for measuring time between pulses in channels | I have two BaF2 detectors with PMT
connected to Ch1 and Ch2. At this time Im
using external triger module to start DRS4. |
|
157
|
Thu Mar 1 19:22:26 2012 |
Stefan Ritt | DRS4- analog pulse counting |
|
|
156
|
Wed Feb 29 06:46:47 2012 |
Sonal | DRS4- analog pulse counting |
|
|
155
|
Fri Feb 24 15:52:43 2012 |
Stefan Ritt | DRS4- analog pulse counting |
|
|
154
|
Wed Feb 22 11:36:51 2012 |
sonal | DRS4- analog pulse counting | Hello
Sir,
|
|
153
|
Wed Feb 15 18:08:13 2012 |
Yuji Iwai | Evaluation Board v4 Trigger/Clock Connectors | Quick question - what type of connectors
are used for the trigger and clock in/out
on the v4 eval board? |
|
152
|
Mon Feb 6 08:15:38 2012 |
Stefan Ritt | what sort of detectors for physical experiment the DRS4 used? |
|
|
151
|
Sat Feb 4 11:59:26 2012 |
Zhongwei Du | what sort of detectors for physical experiment the DRS4 used? | Hello.
We are designing a waveform
sampling board for Si strip array detector |
|
150
|
Tue Jan 31 08:10:37 2012 |
Stefan Ritt | IEEE Real Time 2012 Call for Abstracts | Hello,
I'm co-organizing the upcoming Real
Time Conference, which covers also fields |
|
149
|
Thu Jan 26 10:05:57 2012 |
Ravindra Raghunath Shinde | DRS4 Rev2.0 for analog pulse counting |
|
|
148
|
Thu Jan 26 09:49:38 2012 |
Stefan Ritt | DRS4 Rev2.0 for analog pulse counting |
|
|
147
|
Thu Jan 26 09:44:34 2012 |
Ravindra Raghunath Shinde | DRS4 Rev2.0 for analog pulse counting |
|
|
146
|
Thu Jan 26 09:15:42 2012 |
Stefan Ritt | DRS4 Rev2.0 for analog pulse counting |
|
|
145
|
Thu Jan 26 09:12:03 2012 |
Ravindra Raghunath Shinde | DRS4 Rev2.0 for analog pulse counting | Hello,
We are using DRS4 Rev.2.0 board.
We want to measure number of pulses |
|
144
|
Fri Jan 20 23:50:39 2012 |
Heejong Kim | drs_exam.cpp for evaluation board version 4 |
|
|
143
|
Fri Jan 20 08:09:38 2012 |
Stefan Ritt | drs_exam.cpp for evaluation board version 4 |
|
|
142
|
Thu Jan 19 23:26:26 2012 |
Heejong Kim | drs_exam.cpp for evaluation board version 4 | Hello,
I'm using DRS4 evaluation board version4
in Linux (Scientific Linux 5). |
|
141
|
Wed Dec 14 08:55:29 2011 |
Stefan Ritt | Synchronization Delay in the Firmware for 8051 Controller |
|
|
140
|
Wed Dec 14 00:44:37 2011 |
Hao Huan | Synchronization Delay in the Firmware for 8051 Controller | Hi Stefan,
I have a question
regarding the DRS 4 evaluation board firmware |
|
139
|
Mon Dec 12 16:43:04 2011 |
Stefan Ritt | DC coupled DRS4 input stage | In the attachement you will find a working
DC-coupled input stage to the DRS4 chip.
The bandwidth of this design is about 700 |
|
138
|
Fri Dec 9 17:45:48 2011 |
Michael Büker | Fixes to DOScreen.cpp for recent built on linux | > I was just building version 3.1.0 and ran
into some problems in DOScreen.cpp. Basically
the conversions from
|
|
137
|
Tue Nov 1 11:07:02 2011 |
Stefan Ritt | How to link PMT |
|
|
136
|
Mon Oct 31 09:15:02 2011 |
Zhongwei Du | How to link PMT | I want to measure the signal from PMT .
But it is a current signal, should i just
put a series resistance, or use a amplifier |
|
135
|
Mon Oct 24 10:30:15 2011 |
Stefan Ritt | Phase Shift for ADC Readout |
|
|
134
|
Sun Oct 23 23:32:28 2011 |
Hao Huan | Phase Shift for ADC Readout | Dear Dr. Ritt,
In the DRS 4 datasheet
it is recommended to sample the analog output |
|
133
|
Sat Oct 22 00:40:02 2011 |
Stefan Ritt | DRS4 eval board: readout rate |
|
|
132
|
Sat Oct 15 04:45:25 2011 |
Aurelien Bouvier | DRS4 eval board: readout rate | Hi,
Our setup uses a DRS4 evaluation
board (version 2.0). |
|
131
|
Mon Sep 19 08:53:22 2011 |
Stefan Ritt | compilation error for version 4.0.0 on linux |
|
|
130
|
Fri Sep 16 22:06:07 2011 |
Andriy Zatserklyaniy | compilation error for version 4.0.0 on linux | Hi Stefan,
When I compiled DRS4 software version
4.0.0 on Linux (Debian Squeeze) I got this |
|
129
|
Fri Sep 9 09:31:33 2011 |
Stefan Ritt | DRS4 and AD9222 |
|
|
128
|
Fri Sep 9 09:28:57 2011 |
Guillaume Blanchard | DRS4 and AD9222 | Thank you for your
answers, |
|
127
|
Wed Sep 7 17:28:25 2011 |
Hannes Friederich | DRS4 and AD9222 |
|
|
126
|
Wed Sep 7 16:56:43 2011 |
Stefan Ritt | DRS4 and AD9222 |
|
|
125
|
Wed Sep 7 16:45:17 2011 |
Guillaume Blanchard | DRS4 and AD9222 |
Normal
0
21
false
false
false
|
|
124
|
Wed Jul 13 04:26:52 2011 |
Stefan Ritt | Fixed Patter Timing Jitter |
|
|
123
|
Tue Jul 12 09:49:08 2011 |
Jinhong Wang | Fixed Patter Timing Jitter |
|
|
122
|
Tue Jul 5 10:09:43 2011 |
Stefan Ritt | Fixed Patter Timing Jitter |
|
|
121
|
Mon Jul 4 05:06:00 2011 |
Jinhong Wang | Fixed Patter Timing Jitter |
|
|
120
|
Thu Jun 2 21:01:29 2011 |
Stefan Ritt | Removing spikes |
|
|
119
|
Wed Jun 1 09:57:43 2011 |
Martin Petriska | Removing spikes | I have DSR4 eval board. Found that there
are spikes in channels. Procedure Osc::RemoveSpikes
to remove them looks litlle dificult. There |
|
118
|
Fri Apr 15 08:28:54 2011 |
Stefan Ritt | Fixes to DOScreen.cpp for recent built on linux | > Hello,
>
> I was just building version 3.1.0 and ran |
|
117
|
Thu Apr 14 18:23:53 2011 |
Bob Hirosky | Fixes to DOScreen.cpp for recent built on linux | Hello,
I was just building version 3.1.0 and ran |
|
116
|
Fri Feb 25 10:13:51 2011 |
Stefan Ritt | Announcement digital pulse processing workshop | Dear colleague,
if you live not so far from Zurich,
you might be interested in this workshop: |
|
115
|
Mon Feb 21 12:42:33 2011 |
S S Upadhya | how to synchronize Sampling frequency of two evaluation boards |
|
|
114
|
Mon Feb 21 08:10:31 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
|
|
113
|
Sat Feb 19 22:46:35 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
|
|
112
|
Sat Feb 19 17:25:29 2011 |
S S Upadhya | how to synchronize Sampling frequency of two evaluation boards | Dear sir,
We have two evaluation boards of
DRS4. We would like to use 8 inputs to be |
|
111
|
Tue Nov 16 16:38:06 2010 |
Stefan Ritt | Reference design for DRS4 active input buffer |
|
|
110
|
Tue Oct 12 03:53:37 2010 |
Jinhong Wang | Reference design for DRS4 active input buffer |
|
|
107
|
Wed Jul 21 10:58:20 2010 |
Stefan Ritt | ENOB of DRS |
|
|
106
|
Wed Jul 21 10:46:32 2010 |
Jinhong Wang | ENOB of DRS | Hi, Stefan, I see in your ppt "Design
and performance of 6 GSPS waveform digitizing
chip DRS4" , you define DRS4 ENOB as |
|
105
|
Mon Jul 19 12:47:17 2010 |
Stefan Ritt | Fixed Patter Timing Jitter |
|
|
104
|
Mon Jul 19 12:07:04 2010 |
Jinhong Wang | Fixed Patter Timing Jitter | Hi Stefan, can you give some suggestions
on determination of fixed pattern timing
jitter of DRS4? Thanks~ |
|
99
|
Mon Jul 12 16:07:37 2010 |
Stefan Ritt | Announcement evaluation board V3 | Dear DRS4 users,
a new version of the evaluation board
has been designed and is in production now. |
|
98
|
Tue Jun 22 11:37:42 2010 |
Jinhong Wang | Reset of DRS4 |
|
|
97
|
Tue Jun 22 11:35:18 2010 |
Stefan Ritt | Reset of DRS4 |
|
|
96
|
Tue Jun 22 11:29:26 2010 |
Jinhong Wang | Reset of DRS4 |
|
|
95
|
Tue Jun 22 11:02:30 2010 |
Stefan Ritt | Reset of DRS4 |
|
|
94
|
Tue Jun 22 10:50:19 2010 |
Jinhong Wang | Reset of DRS4 | Hi Stefan,
I found
DRS draw a lot of current when applied Reset |
|
93
|
Sat Jun 19 10:09:18 2010 |
Jinhong Wang | DVDD Problem of DRS 4 |
|
|
92
|
Fri Jun 18 11:45:18 2010 |
Stefan Ritt | DVDD Problem of DRS 4 |
|
|
91
|
Fri Jun 18 11:31:20 2010 |
Jinhong Wang | DVDD Problem of DRS 4 |
|
|
88
|
Tue Jun 1 13:36:18 2010 |
Stefan Ritt | High Frequency Input for DRS |
|
|
87
|
Wed May 26 19:18:09 2010 |
Hao Huan | High Frequency Input for DRS | Hi Stefan,
I read in the
DRS datasheet that the bandwidth for the |
|
86
|
Wed May 19 09:16:02 2010 |
Stefan Ritt | DVDD Problem of DRS 4 |
|
|
85
|
Wed May 19 02:24:12 2010 |
Hao Huan | DVDD Problem of DRS 4 |
|
|
84
|
Tue May 18 09:24:02 2010 |
Stefan Ritt | Reference design for DRS4 active input buffer | The design of high frequency differential
input stages with the DRS4 is a challenge,
since the chip draws quite some current at |
|
83
|
Tue May 18 08:23:07 2010 |
Stefan Ritt | DVDD Problem of DRS 4 |
|
|
82
|
Tue May 18 01:47:59 2010 |
Hao Huan | DVDD Problem of DRS 4 |
|
|
81
|
Fri May 14 08:40:14 2010 |
Stefan Ritt | DVDD Problem of DRS 4 |
|
|
80
|
Thu May 13 19:14:27 2010 |
Hao Huan | DVDD Problem of DRS 4 | Hi Stefan,
on our board some
DRS chips draw a lot of current through DVDD |
|
79
|
Wed May 12 16:26:12 2010 |
Stefan Ritt | DRS4 chip model |
|
|
78
|
Wed May 12 11:47:39 2010 |
Jinhong Wang | DRS4 chip model |
|
|
77
|
Thu May 6 08:15:39 2010 |
Stefan Ritt | Random noise spec in datasheet |
|
|
76
|
Wed May 5 22:30:50 2010 |
Ignacio Diéguez Estremera | Random noise spec in datasheet | Hi,
According to DRS4's datasheet, the
random noise is 0.35mVrms. Is this the input |
|
75
|
Tue May 4 16:23:16 2010 |
Ignacio Diéguez Estremera | DRS4 chip model |
|
|
74
|
Tue May 4 11:26:21 2010 |
Stefan Ritt | DRS4 chip model |
|
|
73
|
Mon May 3 23:21:55 2010 |
Ignacio Diéguez Estremera | DRS4 chip model |
|
|
72
|
Mon May 3 17:10:29 2010 |
Stefan Ritt | DRS4 chip model |
|
|
71
|
Mon May 3 17:06:02 2010 |
Ignacio Diéguez Estremera | DRS4 chip model |
|
|
70
|
Mon May 3 11:09:12 2010 |
Stefan Ritt | DRS4 chip model |
|
|
69
|
Sun May 2 18:36:14 2010 |
Ignacio Diéguez Estremera | DRS4 chip model | Hi all,
i'm an electronics engineering student
at UCM (Madrid) working on my master's thesis |
|
68
|
Thu Apr 15 13:48:40 2010 |
Stefan Ritt | ROFS Configuration |
|
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67
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Wed Apr 14 16:34:28 2010 |
Stefan Ritt | version 1.2 evaluation board with firmware 13279? |
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66
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Tue Apr 13 14:15:16 2010 |
Stefan Ritt | Simple example application to read a DRS evaluation board |
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65
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Tue Apr 13 13:56:07 2010 |
Stefan Ritt | Baseline Variation In Data |
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64
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Tue Apr 13 13:12:43 2010 |
Stefan Ritt | evaluation board used like a counter |
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63
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Tue Apr 13 10:45:18 2010 |
lorenzo neri | evaluation board used like a counter | Hi all
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62
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Fri Apr 9 17:14:45 2010 |
Hao Huan | Baseline Variation In Data | Hi Stefan,
when I sample
a constant input with the DRS 4 chip, there |
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61
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Mon Apr 5 17:57:41 2010 |
Heejong Kim | Simple example application to read a DRS evaluation board |
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60
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Mon Apr 5 17:50:39 2010 |
Heejong Kim | version 1.2 evaluation board with firmware 13279? |
Hi, Stefan,
I found that my collaborator
bought 2 older version of evaluation board
before.
They are the version 1.2 in plastics |
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59
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Tue Mar 30 22:57:34 2010 |
Hao Huan | ROFS Configuration | Hi Stefan,
according to the
DRS4 datasheet, if we want an input range |
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58
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Mon Mar 22 09:12:19 2010 |
Stefan Ritt | PLL Loop Filter Configuration |
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57
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Sun Mar 21 02:03:44 2010 |
Hao Huan | PLL Loop Filter Configuration | Hi Stefan,
in the datasheet
it says at 6GSPS the typical loop filter |
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56
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Thu Mar 18 22:10:41 2010 |
Stefan Ritt | Serial Interface Frequency of the DRS Chip |
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55
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Thu Mar 18 21:38:10 2010 |
Hao Huan | Serial Interface Frequency of the DRS Chip |
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54
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Fri Mar 12 08:04:44 2010 |
Stefan Ritt | Input Bandwidth of the DRS Chip |
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53
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Thu Mar 11 21:37:32 2010 |
Hao Huan | Input Bandwidth of the DRS Chip | Hi Stefan,
I read in the
DRS datasheet that the input bandwidth if |
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52
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Thu Mar 11 11:45:52 2010 |
Stefan Ritt | Readout of DRS Data |
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51
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Wed Mar 10 10:07:28 2010 |
Stefan Ritt | Serial Interface Frequency of the DRS Chip |
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50
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Tue Mar 9 23:28:45 2010 |
Hao Huan | Serial Interface Frequency of the DRS Chip | Hi Stefan,
in the DRS4 datasheet
I read that the optimal frequency for SRCLK |
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49
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Fri Mar 5 23:29:04 2010 |
Hao Huan | Readout of DRS Data |
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48
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Thu Mar 4 19:14:10 2010 |
Hao Huan | Readout of DRS Data | Hi Stefan,
thanks to your
help I can now successfully keep the Domino |
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47
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Wed Mar 3 17:49:30 2010 |
Stefan Ritt | Initialization of the Domino Circuit |
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46
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Wed Mar 3 17:36:31 2010 |
Hao Huan | Initialization of the Domino Circuit | Hi Stefan,
I read in the
datasheet that every time after power up |
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45
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Wed Mar 3 14:37:40 2010 |
Stefan Ritt | PLLLCK signal of DRS4 |
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44
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Mon Feb 22 17:23:59 2010 |
Hao Huan | PLLLCK signal of DRS4 |
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43
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Sun Feb 21 20:33:57 2010 |
Stefan Ritt | PLLLCK signal of DRS4 |
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42
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Sun Feb 21 20:27:46 2010 |
Hao Huan | PLLLCK signal of DRS4 |
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41
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Sun Feb 21 13:47:03 2010 |
Stefan Ritt | PLLLCK signal of DRS4 |
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40
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Sun Feb 21 13:41:35 2010 |
Stefan Ritt | Real Time Conference 2010 | Hello,
may I draw your attention to the
upcoming Real Time Conference 2010, taking |
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39
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Sun Feb 21 00:46:01 2010 |
Hao Huan | PLLLCK signal of DRS4 |
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38
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Sat Feb 20 09:54:48 2010 |
Stefan Ritt | PLLLCK signal of DRS4 |
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37
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Sat Feb 20 01:56:05 2010 |
Hao Huan | PLLLCK signal of DRS4 | Hi Stefan,
in the latest
DRS4 datasheet I only saw your data of the |
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36
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Tue Feb 16 09:38:59 2010 |
Stefan Ritt | Problem reading oscilloscope binary waveform output |
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35
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Mon Feb 15 19:43:34 2010 |
Ron Grazioso | Problem reading oscilloscope binary waveform output | I have saved some waveforms using the oscilloscope
application in both binary and xml.
I can see that the xml file gives me proper |
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34
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Wed Feb 10 15:35:09 2010 |
Stefan Ritt | Hello |
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33
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Wed Feb 10 02:57:55 2010 |
pepe sanchez lopez | Hello | hello i am an student and i want to do
my final project with drs4 board and i really
can´t find how to open waveform file |
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32
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Mon Feb 1 08:30:42 2010 |
Stefan Ritt | Failure In Flashing Xilinx PROM |
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31
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Sun Jan 31 23:52:15 2010 |
Hao Huan | Failure In Flashing Xilinx PROM | Hi Stefan,
I have an old-version
DRS4 evaluation board which doesn't have |
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30
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Mon Jan 11 16:32:21 2010 |
Stefan Ritt | normal_mode_in_drs_exam.cpp |
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29
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Wed Dec 30 14:28:33 2009 |
aliyilmaz | normal_mode_in_drs_exam.cpp | Dear Mr. S. Ritt
i am Ms.
student , am working with your DRS4 board |
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28
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Tue Dec 22 09:07:27 2009 |
Stefan Ritt | Trigger of DRS4 |
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27
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Tue Dec 22 01:30:55 2009 |
Jinhong Wang | Trigger of DRS4 |
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26
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Mon Dec 21 16:52:08 2009 |
Stefan Ritt | Trigger of DRS4 |
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25
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Mon Dec 21 10:17:05 2009 |
Jinhong Wang | Trigger of DRS4 |
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24
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Tue Dec 15 14:38:09 2009 |
Stefan Ritt | Trigger of DRS4 |
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23
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Mon Dec 14 10:14:16 2009 |
Jinhong Wang | Trigger of DRS4 | Dear Mr. S. Ritt
The
following is my confusion about the |
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22
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Wed Nov 4 14:42:22 2009 |
Stefan Ritt | outline dimension of DRS4 |
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21
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Fri Oct 30 03:31:54 2009 |
Jinhong Wang | outline dimension of DRS4 | |
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20
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Mon Oct 19 12:46:12 2009 |
Stefan Ritt | output common mode voltage of DRS4 |
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19
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Mon Oct 19 11:26:29 2009 |
Jinhong Wang | output common mode voltage of DRS4 | Hello Mr.
Stifan.Ritt
In
the DSR4 datasheet, it is mentioned that |
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18
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Mon Oct 19 09:13:00 2009 |
Stefan Ritt | BIAS Pin of DRS4 |
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17
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Mon Oct 19 09:06:43 2009 |
Jinhong Wang | BIAS Pin of DRS4 | Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 |
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16
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Fri Oct 16 10:16:10 2009 |
Stefan Ritt | DSR4 Full Readout Mode |
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15
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Fri Oct 16 09:51:03 2009 |
Jinhong Wang | DSR4 Full Readout Mode | Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed |
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14
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Wed Oct 14 23:53:05 2009 |
Armin Kolb | DRS_exam using USB Evaluation Board with OS X | For the users using a Macintosh,
after several hours the Evaluation
Board is working on my Macintosh (intel). |
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13
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Wed Oct 7 17:58:20 2009 |
Stefan Ritt | VDD switch off speed | It turned out that the VDD switch off speed
plays some important role. On our VME board,
we have a linear regulator, then a 4.7 uF |
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12
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Tue Oct 6 11:20:39 2009 |
Stefan Ritt | VDD instability | It has turned out that the stability of
the AVDD and DVDD power supplies for the
DRS4 are very critical. On the evaluation |
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11
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Thu Jul 9 09:11:03 2009 |
Stefan Ritt | Current problems with drs_exam.cpp | The current version of the DRS readout
example program drs_exam.cpp has two problems:
The sampling frequency |
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10
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Tue Jul 7 16:39:57 2009 |
Stefan Ritt | Power up problem and remedy | Maybe some of you have experienced that
the DRS4 chip can get pretty hot after power
up. After it's initialized the first time, |
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9
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Wed Jun 10 12:46:43 2009 |
Stefan Ritt | Input range switch added in Version 2.1.3 | A new software verison for the DRS4
Evaluation Board has been has been released.
Version 2.1.3 adds a switch for the input |
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8
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Wed Apr 29 07:57:33 2009 |
Stefan Ritt | Simple example application to read a DRS evaluation board |
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7
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Tue Apr 28 11:44:07 2009 |
Stefan Ritt | Simple example application to read a DRS evaluation board | Several people asked for s simple application
to guide them in writing their own application
to read out a DRS board. Such an application |
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6
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Mon Apr 27 15:09:49 2009 |
Stefan Ritt | Amplitude and Timing calibration for DRS4 Evaluation Board | This is a quick notification to all users
of the current DRS4 evaluation board.
As you all know, the DRS4 chip needs |
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5
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Mon Feb 23 09:24:24 2009 |
Stefan Ritt | Rise-time measurements | Many applications using the DRS4 need to
measure fast rising signals, like for PMTs
or MCPs. This short note shows the minimal |
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4
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Wed Feb 11 12:21:07 2009 |
Stefan Ritt | Corrected datasheet Rev. 0.8 | Please note the new datasheet Rev.
0.8 available from the DRS web site. It fixes
the label of pin #76, which was AGND but |
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3
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Wed Jan 14 13:41:44 2009 |
Stefan Ritt | External Trigger Input requirements |
Another tricky issue comes from the
fact that the external TTL trigger and the |
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2
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Wed Jan 14 12:02:04 2009 |
Stefan Ritt | External Trigger Input requirements | Several people mentioned that the external
trigger input (TTL) does not work on the
DRS4 Evaluation Board Rev. 1.1. This is not |
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1
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Mon Dec 15 13:37:38 2008 |
Stefan Ritt | Welcome | Welcome to the DRS4 Discussion Forum.
This forum contains information and discussions
related to the DRS4 chip. Please subscribe |
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